mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-08-18 22:42:23 +00:00
shader: implement BUFFER_ATOMIC_FMAX
This commit is contained in:
nmzik
@@ -85,6 +85,7 @@ bool InstructionMaySplitSpirvBlock(const IR::Instruction& inst) {
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case IR::Opcode::AtomicOrU32:
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case IR::Opcode::AtomicXorU32:
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case IR::Opcode::AtomicFMinF32:
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case IR::Opcode::AtomicFMaxF32:
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case IR::Opcode::FlatLoadUbyte:
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case IR::Opcode::FlatLoadSbyte:
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case IR::Opcode::FlatLoadUshort:
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@@ -58,6 +58,7 @@ constexpr MemoryOpcodeInfo MUBUF_OPS[] = {
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{0x3au, Opcode::BufferAtomicOr, 1, 32},
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{0x3bu, Opcode::BufferAtomicXor, 1, 32},
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{0x3fu, Opcode::BufferAtomicFMin, 1, 32},
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{0x40u, Opcode::BufferAtomicFMax, 1, 32},
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};
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constexpr MemoryOpcodeInfo MTBUF_OPS[] = {
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@@ -836,6 +836,7 @@ std::string OpcodeToString(Opcode opcode) {
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case Opcode::BufferAtomicOr: return "buffer_atomic_or";
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case Opcode::BufferAtomicXor: return "buffer_atomic_xor";
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case Opcode::BufferAtomicFMin: return "buffer_atomic_fmin";
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case Opcode::BufferAtomicFMax: return "buffer_atomic_fmax";
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case Opcode::FlatLoadUbyte: return "flat_load_ubyte";
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case Opcode::FlatLoadSbyte: return "flat_load_sbyte";
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case Opcode::FlatLoadUshort: return "flat_load_ushort";
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@@ -1127,6 +1128,7 @@ std::string InstructionToString(const Instruction& inst) {
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case Opcode::BufferAtomicOr:
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case Opcode::BufferAtomicXor:
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case Opcode::BufferAtomicFMin:
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case Opcode::BufferAtomicFMax:
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case Opcode::BufferLoadSbyte:
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case Opcode::BufferLoadSshort:
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case Opcode::FlatLoadUbyte:
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@@ -435,6 +435,7 @@ enum class Opcode {
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BufferAtomicOr,
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BufferAtomicXor,
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BufferAtomicFMin,
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BufferAtomicFMax,
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FlatLoadUbyte,
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FlatLoadSbyte,
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FlatLoadUshort,
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@@ -132,7 +132,8 @@ bool IsAtomic(IR::Opcode op) {
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case IR::Opcode::AtomicAndU32:
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case IR::Opcode::AtomicOrU32:
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case IR::Opcode::AtomicXorU32:
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case IR::Opcode::AtomicFMinF32: return true;
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case IR::Opcode::AtomicFMinF32:
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case IR::Opcode::AtomicFMaxF32: return true;
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default: return false;
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}
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}
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@@ -142,6 +143,9 @@ uint32_t BufferAddressOperandCount(const IR::Instruction& inst) {
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}
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bool ValidateInstructionContract(const IR::Instruction& inst, std::string* error) {
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if (static_cast<size_t>(inst.op) >= static_cast<size_t>(IR::Opcode::Count)) {
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return Fail(error, "IR instruction opcode is out of range");
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}
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if (inst.src_count > std::size(inst.src)) {
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return Fail(error, "instruction source count exceeds fixed IR storage");
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}
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@@ -201,6 +205,12 @@ bool ValidateInstructionContract(const IR::Instruction& inst, std::string* error
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inst.src_count != 2)) {
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return Fail(error, "storage image instruction has an invalid resource class");
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}
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const auto float_atomic =
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inst.op == IR::Opcode::AtomicFMinF32 || inst.op == IR::Opcode::AtomicFMaxF32;
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if (float_atomic &&
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(kind != IR::ResourceKind::Buffer || inst.src_count != buffer_address_count + 1u)) {
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return Fail(error, "floating-point atomic instruction must target a buffer");
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}
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if (IsAtomic(inst.op) &&
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!((kind == IR::ResourceKind::Buffer && inst.src_count == buffer_address_count + 1u) ||
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((kind == IR::ResourceKind::Lds || kind == IR::ResourceKind::Gds) &&
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@@ -489,6 +499,13 @@ bool EmitProgram(const IR::Program& program, const IR::ResourceSnapshot& resourc
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AllocateBlockLabels(state, program);
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AllocateDispatcherState(state, program);
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EmitFunction(state, program);
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if (state.unsupported_ir_instruction) {
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char pc[9] {};
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std::snprintf(pc, sizeof(pc), "%08x", state.unsupported_ir_pc);
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return Fail(error, "SPIR-V emitter has no handler for IR opcode " +
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std::string(IR::OpcodeName(state.unsupported_ir_opcode)) +
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" at pc 0x" + pc);
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}
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ReportReserveExceeded(program, "registers", state.registers.size());
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ReportReserveExceeded(program, "inputs", state.inputs.size());
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@@ -778,6 +778,9 @@ void EmitInstruction(EmitterState& state, const IR::Instruction& inst) {
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case IR::Opcode::AtomicFMinF32:
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EmitGuardedByExec(state, [&]() { EmitAtomicFMinF32(state, inst); });
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break;
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case IR::Opcode::AtomicFMaxF32:
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EmitGuardedByExec(state, [&]() { EmitAtomicFMaxF32(state, inst); });
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break;
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case IR::Opcode::FlatLoadUbyte: EmitFlatLoadUbyte(state, inst); break;
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case IR::Opcode::FlatLoadSbyte: EmitFlatLoadSbyte(state, inst); break;
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case IR::Opcode::FlatLoadUshort: EmitFlatLoadUshort(state, inst); break;
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@@ -854,7 +857,13 @@ void EmitInstruction(EmitterState& state, const IR::Instruction& inst) {
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}
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EmitGuardedByExec(state, [&]() { EmitExport(state, inst); });
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break;
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default: break;
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default:
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if (!state.unsupported_ir_instruction) {
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state.unsupported_ir_instruction = true;
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state.unsupported_ir_opcode = inst.op;
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state.unsupported_ir_pc = inst.pc;
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}
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break;
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}
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}
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@@ -414,6 +414,9 @@ struct EmitterState {
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bool needs_image_gather_extended = false;
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bool needs_function_lds = false;
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bool needs_pixel_valid_mask = false;
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bool unsupported_ir_instruction = false;
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IR::Opcode unsupported_ir_opcode = IR::Opcode::Count;
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uint32_t unsupported_ir_pc = 0;
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std::vector<RegisterBinding> registers;
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std::vector<InputBinding> inputs;
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std::vector<OutputBinding> outputs;
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@@ -1012,6 +1015,7 @@ void EmitDeviceAtomicMemoryBarrier(EmitterState& state);
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void EmitAtomicU32(EmitterState& state, const IR::Instruction& inst, uint32_t opcode);
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void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst);
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void EmitAtomicFMaxF32(EmitterState& state, const IR::Instruction& inst);
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void EmitSLoadDword(EmitterState& state, const IR::Instruction& inst);
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@@ -1184,7 +1184,8 @@ void EmitAtomicU32(EmitterState& state, const IR::Instruction& inst, uint32_t op
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namespace {
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uint32_t EmitF32BitsOrderedLessThan(EmitterState& state, uint32_t lhs_bits, uint32_t rhs_bits) {
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uint32_t EmitF32BitsOrderedCompare(EmitterState& state, uint32_t lhs_bits, uint32_t rhs_bits,
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uint32_t comparison_opcode) {
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struct ClassifiedBits {
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uint32_t nan = 0;
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uint32_t zero = 0;
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@@ -1219,14 +1220,13 @@ uint32_t EmitF32BitsOrderedLessThan(EmitterState& state, uint32_t lhs_bits, uint
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const auto both_zero = EmitLogicalAndBool(state, lhs.zero, rhs.zero);
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const auto ordered_nonzero =
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EmitLogicalNotBool(state, EmitLogicalOrBool(state, any_nan, both_zero));
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const auto less = state.builder.AllocateId();
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state.builder.AddFunction({OpULessThan, state.bool_type, less, lhs.key, rhs.key});
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return EmitLogicalAndBool(state, ordered_nonzero, less);
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const auto comparison = state.builder.AllocateId();
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state.builder.AddFunction({comparison_opcode, state.bool_type, comparison, lhs.key, rhs.key});
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return EmitLogicalAndBool(state, ordered_nonzero, comparison);
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}
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} // namespace
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void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst) {
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void EmitAtomicFMinMaxF32(EmitterState& state, const IR::Instruction& inst,
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uint32_t comparison_opcode) {
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const auto index =
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EmitMemoryDwordIndex(state, inst, inst.memory, 1, AddressSourceCount(inst, 1));
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const auto in_bounds = EmitStorageBufferElementInBounds(state, inst.memory, index, inst.pc);
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@@ -1235,15 +1235,26 @@ void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst) {
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const auto pointer = EmitStorageBufferElementPointer(state, inst.memory, index, inst.pc);
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return EmitAtomicUpdateU32(state, pointer, inst.memory.kind, [&](uint32_t old_u32) {
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const auto replace_old = state.builder.AllocateId();
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const auto less = EmitF32BitsOrderedLessThan(state, src_u32, old_u32);
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const auto replace =
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EmitF32BitsOrderedCompare(state, src_u32, old_u32, comparison_opcode);
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state.builder.AddFunction(
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{OpSelect, state.uint_type, replace_old, less, src_u32, old_u32});
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{OpSelect, state.uint_type, replace_old, replace, src_u32, old_u32});
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return replace_old;
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});
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});
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EmitStoreU32(state, inst.dst, old);
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}
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} // namespace
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void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst) {
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EmitAtomicFMinMaxF32(state, inst, OpULessThan);
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}
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void EmitAtomicFMaxF32(EmitterState& state, const IR::Instruction& inst) {
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EmitAtomicFMinMaxF32(state, inst, OpUGreaterThan);
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}
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void EmitSLoadDword(EmitterState& state, const IR::Instruction& inst) {
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if (state.address_memory_variable == 0) {
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ExitDescriptorBindingFailure(state, IR::DescriptorBindingKind::AddressMemory,
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@@ -31,7 +31,8 @@ bool IsAtomic(Opcode op) {
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case Opcode::AtomicAndU32:
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case Opcode::AtomicOrU32:
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case Opcode::AtomicXorU32:
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case Opcode::AtomicFMinF32: return true;
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case Opcode::AtomicFMinF32:
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case Opcode::AtomicFMaxF32: return true;
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default: return false;
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}
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}
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@@ -975,7 +975,12 @@ bool LowerControlInstruction(const Decoder::Instruction& decoded, BasicBlock& bl
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return LowerControlMarker(decoded, block, Opcode::TtraceData, true, error);
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case Decoder::Opcode::SInstPrefetch:
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return LowerControlMarker(decoded, block, Opcode::InstPrefetch, true, error);
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default: return false;
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default:
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if (error != nullptr) {
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*error = fmt::format("control opcode has no specialized IR lowering: {}",
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Decoder::OpcodeToString(decoded.opcode));
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}
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return false;
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}
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}
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@@ -1064,6 +1069,18 @@ bool IsTerminatorOpcode(Decoder::Opcode opcode) {
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bool LowerImplemented(const Decoder::Instruction& decoded, BasicBlock& block, std::string* error);
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bool IsMemoryFamily(Decoder::Family family) {
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switch (family) {
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case Decoder::Family::SMEM:
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case Decoder::Family::MUBUF:
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case Decoder::Family::MTBUF:
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case Decoder::Family::FLAT:
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case Decoder::Family::DS:
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case Decoder::Family::MIMG: return true;
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default: return false;
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}
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}
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bool LowerDecodedInstruction(const Decoder::Instruction& inst, BasicBlock& block,
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std::string* error) {
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switch (inst.opcode) {
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@@ -1117,6 +1134,15 @@ bool LowerDecodedInstruction(const Decoder::Instruction& inst, BasicBlock& block
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if (IsMemoryOpcode(inst.opcode)) {
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return LowerMemoryInstruction(inst, block, error);
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}
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// Memory instructions require specialized lowering to populate MemoryInfo. Never let a
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// newly decoded memory-family opcode fall through to generic register-only IR.
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if (IsMemoryFamily(inst.family)) {
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if (error != nullptr) {
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*error = fmt::format("decoded memory-family opcode has no specialized IR lowering: {}",
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Decoder::OpcodeToString(inst.opcode));
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}
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return false;
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}
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if (ScalarShiftLeftAddAmount(inst.opcode) != 0) {
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return LowerScalarShiftLeftAdd(inst, block, error);
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}
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@@ -571,6 +571,8 @@ bool LowerMemoryInstruction(const Decoder::Instruction& decoded, BasicBlock& blo
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicXorU32, error);
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case Decoder::Opcode::BufferAtomicFMin:
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicFMinF32, error);
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case Decoder::Opcode::BufferAtomicFMax:
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicFMaxF32, error);
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case Decoder::Opcode::FlatLoadUbyte:
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case Decoder::Opcode::FlatLoadSbyte:
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case Decoder::Opcode::FlatLoadUshort:
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@@ -675,7 +677,12 @@ bool LowerMemoryInstruction(const Decoder::Instruction& decoded, BasicBlock& blo
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case Decoder::Opcode::ImageAtomicAnd:
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case Decoder::Opcode::ImageAtomicOr:
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case Decoder::Opcode::ImageAtomicXor: return LowerImageAtomicU32(decoded, block, error);
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default: return false;
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default:
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if (error != nullptr) {
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*error = fmt::format("memory opcode has no specialized IR lowering: {}",
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Decoder::OpcodeToString(decoded.opcode));
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}
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return false;
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}
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}
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@@ -732,6 +739,7 @@ bool IsMemoryOpcode(Decoder::Opcode opcode) {
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case Decoder::Opcode::BufferAtomicOr:
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case Decoder::Opcode::BufferAtomicXor:
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case Decoder::Opcode::BufferAtomicFMin:
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case Decoder::Opcode::BufferAtomicFMax:
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case Decoder::Opcode::FlatLoadUbyte:
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case Decoder::Opcode::FlatLoadSbyte:
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case Decoder::Opcode::FlatLoadUshort:
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@@ -353,6 +353,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::BufferAtomicOr, Opcode::AtomicOrU32},
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{Decoder::Opcode::BufferAtomicXor, Opcode::AtomicXorU32},
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{Decoder::Opcode::BufferAtomicFMin, Opcode::AtomicFMinF32},
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{Decoder::Opcode::BufferAtomicFMax, Opcode::AtomicFMaxF32},
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{Decoder::Opcode::FlatLoadUbyte, Opcode::FlatLoadUbyte},
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{Decoder::Opcode::FlatLoadSbyte, Opcode::FlatLoadSbyte},
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{Decoder::Opcode::FlatLoadSshort, Opcode::FlatLoadSshort},
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@@ -308,6 +308,7 @@ IR_OPCODE(AtomicAndU32, General)
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IR_OPCODE(AtomicOrU32, General)
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IR_OPCODE(AtomicXorU32, General)
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IR_OPCODE(AtomicFMinF32, General)
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IR_OPCODE(AtomicFMaxF32, General)
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IR_OPCODE(FlatLoadUbyte, General)
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IR_OPCODE(FlatLoadSbyte, General)
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IR_OPCODE(FlatLoadUshort, General)
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@@ -9051,6 +9051,7 @@ CoverageClass ClassifyOpcode(ShaderOpcode opcode, const std::set<ShaderOpcode>&
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case Opcode::BufferAtomicOr:
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case Opcode::BufferAtomicXor:
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case Opcode::BufferAtomicFMin:
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case Opcode::BufferAtomicFMax:
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case Opcode::FlatLoadUbyte:
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case Opcode::FlatLoadSbyte:
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case Opcode::FlatLoadUshort:
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@@ -14017,6 +14018,105 @@ TestCase BufferAtomicFMinContendedWorkgroup() {
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return test;
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}
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TestCase BufferAtomicFMaxExactRawGlcModes() {
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using O = ShaderOpcode;
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std::vector<u32> code;
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AppendVMovLiteral(&code, 3, 0x40000000u); // 2.0
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code.push_back(0xe100000cu);
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code.push_back(0x80010300u); // exact failing buffer_atomic_fmax v3, offset 12, GLC=0
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AppendStoreVgpr(&code, 3, 4);
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AppendVMovLiteral(&code, 0, 0x40800000u); // 4.0
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code.push_back(0xe100400cu);
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code.push_back(0x80010000u); // same address with GLC=1
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AppendStoreVgpr(&code, 0, 5);
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AppendEnd(&code);
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TestCase test;
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test.name = "BufferAtomicFMaxExactRawGlcModes";
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test.code = code;
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test.initial = {0, 0, 0, 0x3f800000u, 0, 0}; // memory[3] = 1.0
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test.expected = {0, 0, 0, 0x40800000u, 0x40000000u, 0x40000000u};
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test.opcodes = {O::VMovB32, O::BufferAtomicFMax, O::BufferStoreDword, O::SEndpgm};
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const auto descriptor =
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MakeStructuredStorageBufferData(0, static_cast<u32>(test.initial.size() * sizeof(u32)));
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std::copy_n(descriptor.begin(), 4, test.user_data.begin() + 4);
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test.user_data[50] = 1u << 20u;
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test.has_user_data = true;
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return test;
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}
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TestCase BufferAtomicFMaxSpecialValues() {
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using O = ShaderOpcode;
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const u32 values[] = {
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0x40000000u, // 2.0, finite update
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0x40000000u, // 2.0, finite no-update
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0x7f800000u, // incoming +infinity
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0xff800000u, // incoming -infinity
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0x3f800000u, // finite against old +infinity
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0x3f800000u, // finite against old -infinity
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0x3f800000u, // finite against old quiet NaN
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0x7fcabcdeu, // incoming quiet NaN
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0x3f800000u, // finite against old signaling NaN
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0x7faabcdeu, // incoming signaling NaN
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0x00000000u, // +0.0 against old -0.0
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0x80000000u, // -0.0 against old +0.0
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0x80000000u, // -0.0 against a negative denorm
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0x80000001u, // negative denorm against -0.0
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0x00000001u, // positive denorm against +0.0
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0x00000000u, // +0.0 against a positive denorm
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};
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std::vector<u32> code;
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for (u32 i = 0; i < static_cast<u32>(std::size(values)); i++) {
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AppendVMovU32(&code, 20, i * 4u);
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AppendVMovLiteral(&code, i, values[i]);
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AppendBufferStoreOpcode(&code, 0x40, i, 20, true);
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}
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for (u32 i = 0; i < static_cast<u32>(std::size(values)); i++) {
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AppendStoreVgpr(&code, i, i + static_cast<u32>(std::size(values)));
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}
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AppendEnd(&code);
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|
||||
return {"BufferAtomicFMaxSpecialValues",
|
||||
code,
|
||||
{0x3f800000u, 0x40800000u, 0xbf800000u, 0x3f800000u, 0x7f800000u,
|
||||
0xff800000u, 0x7fc12345u, 0x3f800000u, 0x7fa54321u, 0x3f800000u,
|
||||
0x80000000u, 0x00000000u, 0x80000001u, 0x80000000u, 0x00000000u,
|
||||
0x00000001u, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0x40000000u, 0x40800000u, 0x7f800000u, 0x3f800000u, 0x7f800000u,
|
||||
0x3f800000u, 0x7fc12345u, 0x3f800000u, 0x7fa54321u, 0x3f800000u,
|
||||
0x80000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x00000001u,
|
||||
0x00000001u, 0x3f800000u, 0x40800000u, 0xbf800000u, 0x3f800000u,
|
||||
0x7f800000u, 0xff800000u, 0x7fc12345u, 0x3f800000u, 0x7fa54321u,
|
||||
0x3f800000u, 0x80000000u, 0x00000000u, 0x80000001u, 0x80000000u,
|
||||
0x00000000u, 0x00000001u},
|
||||
{O::VMovB32, O::BufferAtomicFMax, O::BufferStoreDword, O::SEndpgm}};
|
||||
}
|
||||
|
||||
TestCase BufferAtomicFMaxContendedWorkgroup() {
|
||||
using O = ShaderOpcode;
|
||||
|
||||
std::vector<u32> code;
|
||||
code.push_back(EncodeVop1(0x06, 1, Vgpr(0))); // v_cvt_f32_u32 v1, thread_id.x
|
||||
AppendVMovU32(&code, 20, 0);
|
||||
AppendBufferStoreOpcode(&code, 0x40, 1, 20);
|
||||
AppendEnd(&code);
|
||||
|
||||
TestCase test;
|
||||
test.name = "BufferAtomicFMaxContendedWorkgroup";
|
||||
test.code = code;
|
||||
test.initial = {0xc2c80000u}; // -100.0
|
||||
test.expected = {0x427c0000u}; // max(-100.0, 0.0 .. 63.0)
|
||||
test.opcodes = {O::VCvtF32U32, O::VMovB32, O::BufferAtomicFMax, O::SEndpgm};
|
||||
test.compute_info.threads_num[0] = 64;
|
||||
test.compute_info.threads_num[1] = 1;
|
||||
test.compute_info.threads_num[2] = 1;
|
||||
test.compute_info.thread_ids_num = 1;
|
||||
test.has_compute_info = true;
|
||||
return test;
|
||||
}
|
||||
|
||||
std::vector<u32> MakeRgbaImage(u32 width, u32 height, u32 value = 0) {
|
||||
return std::vector<u32>(static_cast<size_t>(width) * height * 4u, value);
|
||||
}
|
||||
@@ -15370,6 +15470,9 @@ std::vector<TestCase> MakeCases() {
|
||||
AddCase(BufferAtomicFMinExactRawGlcModes);
|
||||
AddCase(BufferAtomicFMinSpecialValues);
|
||||
AddCase(BufferAtomicFMinContendedWorkgroup);
|
||||
AddCase(BufferAtomicFMaxExactRawGlcModes);
|
||||
AddCase(BufferAtomicFMaxSpecialValues);
|
||||
AddCase(BufferAtomicFMaxContendedWorkgroup);
|
||||
AddCase(ImageLoadVariants);
|
||||
AddCase(ImageLoadR32UintUsesIntegerSampledImage);
|
||||
AddCase(ImageLoad1DUsesScalarCoordinate);
|
||||
|
||||
@@ -2959,6 +2959,15 @@ void TestNewShaderRecompilerIrLookupMissFailsExplicitly() {
|
||||
Check(Common::ContainsStr(error, "no IR lowering"),
|
||||
"missing decoder-to-IR mapping did not report an explicit error");
|
||||
Check(ir.blocks.empty(), "missing decoder-to-IR mapping emitted a fallback IR block");
|
||||
|
||||
decoded.instructions.front().family = ShaderRecompiler::Decoder::Family::MUBUF;
|
||||
decoded.instructions.front().opcode = ShaderRecompiler::Decoder::Opcode::VAddNcU32;
|
||||
error.clear();
|
||||
Check(!ShaderRecompiler::IR::LowerProgram(decoded, cfg, ShaderType::Compute, 64u, ir, &error),
|
||||
"memory-family opcode bypassed specialized memory lowering");
|
||||
Check(Common::ContainsStr(error, "memory-family opcode") &&
|
||||
Common::ContainsStr(error, "specialized IR lowering"),
|
||||
"memory-family lowering bypass did not report an explicit error");
|
||||
}
|
||||
|
||||
void TestNewShaderRecompilerMemoryFamilyLowering() {
|
||||
@@ -4790,6 +4799,8 @@ void TestNewShaderRecompilerAtomicLowering() {
|
||||
EncodeMubuf1(6, 0, 1), // buffer_atomic_xor
|
||||
0xe0fc0000u,
|
||||
0x80010000u, // exact buffer_atomic_fmin v0, s[4:7], 0 (GLC=0)
|
||||
0xe100000cu,
|
||||
0x80010300u, // exact failing buffer_atomic_fmax v3, s[4:7], 12 (GLC=0)
|
||||
EncodeDs0(0x00),
|
||||
EncodeDs1(0, 2, 1), // ds_add_u32
|
||||
EncodeDs0(0x01),
|
||||
@@ -4846,6 +4857,8 @@ void TestNewShaderRecompilerAtomicLowering() {
|
||||
"new decoder did not decode buffer atomic xor");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "buffer_atomic_fmin"),
|
||||
"new decoder did not decode buffer atomic float min");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "buffer_atomic_fmax"),
|
||||
"new decoder did not decode buffer atomic float max");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "ds_add_u32"),
|
||||
"new decoder did not decode DS atomic add");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "ds_sub_u32"),
|
||||
@@ -4880,6 +4893,8 @@ void TestNewShaderRecompilerAtomicLowering() {
|
||||
"buffer atomic xor did not lower to IR");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicFMinF32 null, v0"),
|
||||
"buffer atomic float min did not lower to IR without a GLC return");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicFMaxF32 null, v3"),
|
||||
"buffer atomic float max did not lower to IR without a GLC return");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicAddU32 null, v2"),
|
||||
"DS no-return atomic add did not lower to IR");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicSubU32 null, v10"),
|
||||
@@ -6712,6 +6727,35 @@ void TestNewShaderRecompilerNativeBindingPlan() {
|
||||
rejected_spirv == rejected_before && rejected_error.find("atomic") != std::string::npos,
|
||||
"malformed atomic instruction reached a fatal descriptor path");
|
||||
|
||||
auto malformed_float_atomic = result.program;
|
||||
atomic_inst = FindBufferInstruction(&malformed_float_atomic);
|
||||
Check(atomic_inst != nullptr, "native validation fixture lacks a float atomic candidate");
|
||||
atomic_inst->op = ShaderRecompiler::IR::Opcode::AtomicFMaxF32;
|
||||
atomic_inst->memory.kind = ShaderRecompiler::IR::ResourceKind::Lds;
|
||||
atomic_inst->memory.resource = 0;
|
||||
atomic_inst->src_count = 2;
|
||||
rejected_spirv = rejected_before;
|
||||
rejected_error.clear();
|
||||
Check(!ShaderRecompiler::Spirv::EmitProgram(malformed_float_atomic, result.resources, nullptr,
|
||||
nullptr, nullptr, rejected_spirv,
|
||||
&rejected_error) &&
|
||||
rejected_spirv == rejected_before &&
|
||||
rejected_error.find("floating-point atomic") != std::string::npos,
|
||||
"buffer-only floating-point atomic accepted a non-buffer resource");
|
||||
|
||||
auto invalid_ir_opcode = result.program;
|
||||
Check(!invalid_ir_opcode.blocks.empty() && !invalid_ir_opcode.blocks.front().instructions.empty(),
|
||||
"native validation fixture lacks an invalid-opcode candidate");
|
||||
invalid_ir_opcode.blocks.front().instructions.front().op =
|
||||
ShaderRecompiler::IR::Opcode::Count;
|
||||
rejected_spirv = rejected_before;
|
||||
rejected_error.clear();
|
||||
Check(!ShaderRecompiler::Spirv::EmitProgram(invalid_ir_opcode, result.resources, nullptr, nullptr,
|
||||
nullptr, rejected_spirv, &rejected_error) &&
|
||||
rejected_spirv == rejected_before &&
|
||||
rejected_error.find("opcode is out of range") != std::string::npos,
|
||||
"out-of-range IR opcode was not rejected transactionally before emission");
|
||||
|
||||
auto overwide_atomic = result.program;
|
||||
atomic_inst = FindBufferInstruction(&overwide_atomic);
|
||||
Check(atomic_inst != nullptr, "native validation fixture lacks an overwide atomic candidate");
|
||||
|
||||
Reference in New Issue
Block a user