mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-08-18 22:42:23 +00:00
shader: implement BUFFER_ATOMIC_FMIN, unhandled IR opcode now fails
This commit is contained in:
nmzik
@@ -84,6 +84,7 @@ bool InstructionMaySplitSpirvBlock(const IR::Instruction& inst) {
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case IR::Opcode::AtomicAndU32:
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case IR::Opcode::AtomicOrU32:
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case IR::Opcode::AtomicXorU32:
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case IR::Opcode::AtomicFMinF32:
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case IR::Opcode::FlatLoadUbyte:
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case IR::Opcode::FlatLoadSbyte:
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case IR::Opcode::FlatLoadUshort:
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@@ -57,6 +57,7 @@ constexpr MemoryOpcodeInfo MUBUF_OPS[] = {
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{0x39u, Opcode::BufferAtomicAnd, 1, 32},
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{0x3au, Opcode::BufferAtomicOr, 1, 32},
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{0x3bu, Opcode::BufferAtomicXor, 1, 32},
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{0x3fu, Opcode::BufferAtomicFMin, 1, 32},
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};
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constexpr MemoryOpcodeInfo MTBUF_OPS[] = {
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@@ -835,6 +835,7 @@ std::string OpcodeToString(Opcode opcode) {
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case Opcode::BufferAtomicAnd: return "buffer_atomic_and";
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case Opcode::BufferAtomicOr: return "buffer_atomic_or";
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case Opcode::BufferAtomicXor: return "buffer_atomic_xor";
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case Opcode::BufferAtomicFMin: return "buffer_atomic_fmin";
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case Opcode::FlatLoadUbyte: return "flat_load_ubyte";
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case Opcode::FlatLoadSbyte: return "flat_load_sbyte";
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case Opcode::FlatLoadUshort: return "flat_load_ushort";
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@@ -1125,6 +1126,7 @@ std::string InstructionToString(const Instruction& inst) {
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case Opcode::BufferAtomicAnd:
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case Opcode::BufferAtomicOr:
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case Opcode::BufferAtomicXor:
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case Opcode::BufferAtomicFMin:
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case Opcode::BufferLoadSbyte:
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case Opcode::BufferLoadSshort:
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case Opcode::FlatLoadUbyte:
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@@ -434,6 +434,7 @@ enum class Opcode {
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BufferAtomicAnd,
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BufferAtomicOr,
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BufferAtomicXor,
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BufferAtomicFMin,
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FlatLoadUbyte,
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FlatLoadSbyte,
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FlatLoadUshort,
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@@ -131,7 +131,8 @@ bool IsAtomic(IR::Opcode op) {
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case IR::Opcode::AtomicUMaxU32:
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case IR::Opcode::AtomicAndU32:
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case IR::Opcode::AtomicOrU32:
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case IR::Opcode::AtomicXorU32: return true;
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case IR::Opcode::AtomicXorU32:
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case IR::Opcode::AtomicFMinF32: return true;
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default: return false;
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}
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}
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@@ -775,6 +775,9 @@ void EmitInstruction(EmitterState& state, const IR::Instruction& inst) {
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case IR::Opcode::AtomicXorU32:
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EmitGuardedByExec(state, [&]() { EmitAtomicU32(state, inst, OpAtomicXor); });
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break;
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case IR::Opcode::AtomicFMinF32:
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EmitGuardedByExec(state, [&]() { EmitAtomicFMinF32(state, inst); });
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break;
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case IR::Opcode::FlatLoadUbyte: EmitFlatLoadUbyte(state, inst); break;
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case IR::Opcode::FlatLoadSbyte: EmitFlatLoadSbyte(state, inst); break;
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case IR::Opcode::FlatLoadUshort: EmitFlatLoadUshort(state, inst); break;
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@@ -1011,6 +1011,8 @@ void EmitDeviceAtomicMemoryBarrier(EmitterState& state);
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void EmitAtomicU32(EmitterState& state, const IR::Instruction& inst, uint32_t opcode);
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void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst);
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void EmitSLoadDword(EmitterState& state, const IR::Instruction& inst);
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void EmitLoadSrtDword(EmitterState& state, const IR::Instruction& inst);
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@@ -1573,19 +1575,22 @@ uint32_t EmitValueOrZeroIfCondition(EmitterState& state, uint32_t condition, Fn&
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}
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const auto then_label = state.builder.AllocateId();
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const auto then_exit = state.builder.AllocateId();
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const auto else_label = state.builder.AllocateId();
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const auto merge_label = state.builder.AllocateId();
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state.builder.AddFunction({OpSelectionMerge, merge_label, SelectionControlNone});
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state.builder.AddFunction({OpBranchConditional, condition, then_label, else_label});
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state.builder.AddFunction({OpLabel, then_label});
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const auto then_value = fn();
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state.builder.AddFunction({OpBranch, then_exit});
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state.builder.AddFunction({OpLabel, then_exit});
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state.builder.AddFunction({OpBranch, merge_label});
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state.builder.AddFunction({OpLabel, else_label});
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state.builder.AddFunction({OpBranch, merge_label});
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state.builder.AddFunction({OpLabel, merge_label});
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const auto value = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpPhi, state.uint_type, value, then_value, then_label, ConstantU32(state, 0), else_label});
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{OpPhi, state.uint_type, value, then_value, then_exit, ConstantU32(state, 0), else_label});
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return value;
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}
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@@ -640,8 +640,8 @@ void EmitMemoryStoreU32(EmitterState& state, const IR::Instruction& inst, IR::Re
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}
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template <typename Fn>
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void EmitAtomicUpdateU32(EmitterState& state, uint32_t pointer, IR::ResourceKind kind,
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Fn&& desired_value) {
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uint32_t EmitAtomicUpdateU32(EmitterState& state, uint32_t pointer, IR::ResourceKind kind,
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Fn&& desired_value) {
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const auto scope = kind == IR::ResourceKind::Lds ? ScopeWorkgroup : ScopeDevice;
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const auto memory = kind == IR::ResourceKind::Lds ? MemorySemanticsWorkgroupMemory
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: MemorySemanticsUniformMemory;
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@@ -675,6 +675,7 @@ void EmitAtomicUpdateU32(EmitterState& state, uint32_t pointer, IR::ResourceKind
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const auto semantics = MemorySemanticsAcquireRelease | memory;
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state.builder.AddFunction(
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{OpMemoryBarrier, ConstantU32(state, scope), ConstantU32(state, semantics)});
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return observed;
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}
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void EmitMemoryStoreSubDwordU32(EmitterState& state, const IR::Instruction& inst,
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@@ -1181,6 +1182,68 @@ void EmitAtomicU32(EmitterState& state, const IR::Instruction& inst, uint32_t op
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EmitStoreU32(state, inst.dst, old);
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}
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namespace {
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uint32_t EmitF32BitsOrderedLessThan(EmitterState& state, uint32_t lhs_bits, uint32_t rhs_bits) {
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struct ClassifiedBits {
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uint32_t nan = 0;
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uint32_t zero = 0;
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uint32_t key = 0;
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};
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const auto Classify = [&](uint32_t bits) {
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ClassifiedBits cls;
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const auto abs_bits = EmitAndConstant(state, bits, 0x7fffffffu);
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const auto exponent_bits = EmitAndConstant(state, abs_bits, 0x7f800000u);
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const auto mantissa_bits = EmitAndConstant(state, abs_bits, 0x007fffffu);
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const auto exponent_max =
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EmitCompareU32Constant(state, OpIEqual, exponent_bits, 0x7f800000u);
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const auto mantissa_nonzero = EmitCompareU32Constant(state, OpINotEqual, mantissa_bits, 0);
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const auto negative = EmitCompareU32Constant(state, OpINotEqual,
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EmitAndConstant(state, bits, 0x80000000u), 0);
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const auto negative_key = state.builder.AllocateId();
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const auto positive_key = state.builder.AllocateId();
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// Map all non-NaN IEEE-754 encodings to monotonically increasing unsigned keys.
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state.builder.AddFunction({OpNot, state.uint_type, negative_key, bits});
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state.builder.AddFunction(
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{OpBitwiseXor, state.uint_type, positive_key, bits, ConstantU32(state, 0x80000000u)});
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cls.nan = EmitLogicalAndBool(state, exponent_max, mantissa_nonzero);
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cls.zero = EmitCompareU32Constant(state, OpIEqual, abs_bits, 0);
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cls.key = EmitSelectValueU32(state, negative, negative_key, positive_key);
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return cls;
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};
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const auto lhs = Classify(lhs_bits);
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const auto rhs = Classify(rhs_bits);
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const auto any_nan = EmitLogicalOrBool(state, lhs.nan, rhs.nan);
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// The key transform orders -0 below +0, while the floating comparison treats them as equal.
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const auto both_zero = EmitLogicalAndBool(state, lhs.zero, rhs.zero);
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const auto ordered_nonzero =
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EmitLogicalNotBool(state, EmitLogicalOrBool(state, any_nan, both_zero));
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const auto less = state.builder.AllocateId();
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state.builder.AddFunction({OpULessThan, state.bool_type, less, lhs.key, rhs.key});
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return EmitLogicalAndBool(state, ordered_nonzero, less);
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}
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} // namespace
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void EmitAtomicFMinF32(EmitterState& state, const IR::Instruction& inst) {
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const auto index =
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EmitMemoryDwordIndex(state, inst, inst.memory, 1, AddressSourceCount(inst, 1));
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const auto in_bounds = EmitStorageBufferElementInBounds(state, inst.memory, index, inst.pc);
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const auto src_u32 = EmitValueLoad(state, inst.src[0]);
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const auto old = EmitValueOrZeroIfCondition(state, in_bounds, [&]() {
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const auto pointer = EmitStorageBufferElementPointer(state, inst.memory, index, inst.pc);
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return EmitAtomicUpdateU32(state, pointer, inst.memory.kind, [&](uint32_t old_u32) {
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const auto replace_old = state.builder.AllocateId();
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const auto less = EmitF32BitsOrderedLessThan(state, src_u32, old_u32);
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state.builder.AddFunction(
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{OpSelect, state.uint_type, replace_old, less, src_u32, old_u32});
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return replace_old;
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});
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});
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EmitStoreU32(state, inst.dst, old);
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}
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void EmitSLoadDword(EmitterState& state, const IR::Instruction& inst) {
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if (state.address_memory_variable == 0) {
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ExitDescriptorBindingFailure(state, IR::DescriptorBindingKind::AddressMemory,
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@@ -30,7 +30,8 @@ bool IsAtomic(Opcode op) {
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case Opcode::AtomicUMaxU32:
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case Opcode::AtomicAndU32:
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case Opcode::AtomicOrU32:
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case Opcode::AtomicXorU32: return true;
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case Opcode::AtomicXorU32:
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case Opcode::AtomicFMinF32: return true;
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default: return false;
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}
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}
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@@ -569,6 +569,8 @@ bool LowerMemoryInstruction(const Decoder::Instruction& decoded, BasicBlock& blo
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicOrU32, error);
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case Decoder::Opcode::BufferAtomicXor:
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicXorU32, error);
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case Decoder::Opcode::BufferAtomicFMin:
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return LowerBufferAtomicDword(decoded, block, Opcode::AtomicFMinF32, error);
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case Decoder::Opcode::FlatLoadUbyte:
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case Decoder::Opcode::FlatLoadSbyte:
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case Decoder::Opcode::FlatLoadUshort:
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@@ -729,6 +731,7 @@ bool IsMemoryOpcode(Decoder::Opcode opcode) {
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case Decoder::Opcode::BufferAtomicAnd:
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case Decoder::Opcode::BufferAtomicOr:
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case Decoder::Opcode::BufferAtomicXor:
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case Decoder::Opcode::BufferAtomicFMin:
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case Decoder::Opcode::FlatLoadUbyte:
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case Decoder::Opcode::FlatLoadSbyte:
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case Decoder::Opcode::FlatLoadUshort:
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@@ -352,6 +352,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::BufferAtomicAnd, Opcode::AtomicAndU32},
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{Decoder::Opcode::BufferAtomicOr, Opcode::AtomicOrU32},
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{Decoder::Opcode::BufferAtomicXor, Opcode::AtomicXorU32},
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{Decoder::Opcode::BufferAtomicFMin, Opcode::AtomicFMinF32},
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{Decoder::Opcode::FlatLoadUbyte, Opcode::FlatLoadUbyte},
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{Decoder::Opcode::FlatLoadSbyte, Opcode::FlatLoadSbyte},
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{Decoder::Opcode::FlatLoadSshort, Opcode::FlatLoadSshort},
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@@ -307,6 +307,7 @@ IR_OPCODE(AtomicUMaxU32, General)
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IR_OPCODE(AtomicAndU32, General)
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IR_OPCODE(AtomicOrU32, General)
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IR_OPCODE(AtomicXorU32, General)
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IR_OPCODE(AtomicFMinF32, General)
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IR_OPCODE(FlatLoadUbyte, General)
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IR_OPCODE(FlatLoadSbyte, General)
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IR_OPCODE(FlatLoadUshort, General)
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@@ -9050,6 +9050,7 @@ CoverageClass ClassifyOpcode(ShaderOpcode opcode, const std::set<ShaderOpcode>&
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case Opcode::BufferAtomicAnd:
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case Opcode::BufferAtomicOr:
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case Opcode::BufferAtomicXor:
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case Opcode::BufferAtomicFMin:
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case Opcode::FlatLoadUbyte:
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case Opcode::FlatLoadSbyte:
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case Opcode::FlatLoadUshort:
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@@ -13929,6 +13930,93 @@ TestCase BufferAtomicGlc0DoesNotReturnOldValue() {
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{O::VMovB32, O::BufferAtomicAdd, O::BufferStoreDword, O::SEndpgm}};
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}
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TestCase BufferAtomicFMinExactRawGlcModes() {
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using O = ShaderOpcode;
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std::vector<u32> code;
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AppendVMovLiteral(&code, 0, 0x40000000u); // 2.0
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code.push_back(0xe0fc0000u);
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code.push_back(0x80010000u); // exact failing buffer_atomic_fmin, GLC=0
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AppendStoreVgpr(&code, 0, 1);
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AppendVMovLiteral(&code, 0, 0x3f800000u); // 1.0
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code.push_back(0xe0fc4000u);
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code.push_back(0x80010000u); // same instruction with GLC=1
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AppendStoreVgpr(&code, 0, 2);
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AppendEnd(&code);
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TestCase test;
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test.name = "BufferAtomicFMinExactRawGlcModes";
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test.code = code;
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test.initial = {0x40800000u, 0, 0}; // 4.0
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test.expected = {0x3f800000u, 0x40000000u, 0x40000000u};
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test.opcodes = {O::VMovB32, O::BufferAtomicFMin, O::BufferStoreDword, O::SEndpgm};
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const auto descriptor =
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MakeStructuredStorageBufferData(0, static_cast<u32>(test.initial.size() * sizeof(u32)));
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std::copy_n(descriptor.begin(), 4, test.user_data.begin() + 4);
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test.user_data[50] = 1u << 20u;
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test.has_user_data = true;
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return test;
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}
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TestCase BufferAtomicFMinSpecialValues() {
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using O = ShaderOpcode;
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const u32 values[] = {
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0x40000000u, // 2.0
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0x7f800000u, // +infinity
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0xff800000u, // -infinity
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0x3f800000u, // 1.0
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0x7fc00000u, // quiet NaN
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0x00000000u, // +0.0
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0x80000000u, // -0.0
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0x00000000u, // +0.0
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0x80000001u, // smallest negative denorm
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};
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std::vector<u32> code;
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for (u32 i = 0; i < static_cast<u32>(std::size(values)); i++) {
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AppendVMovU32(&code, 20, i * 4u);
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AppendVMovLiteral(&code, i, values[i]);
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AppendBufferStoreOpcode(&code, 0x3f, i, 20, true);
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}
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for (u32 i = 0; i < static_cast<u32>(std::size(values)); i++) {
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AppendStoreVgpr(&code, i, i + static_cast<u32>(std::size(values)));
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}
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AppendEnd(&code);
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return {"BufferAtomicFMinSpecialValues",
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code,
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{0x40800000u, 0xbf800000u, 0x7f800000u, 0x7fc00000u, 0x3f800000u,
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0x80000000u, 0x00000000u, 0x00000001u, 0x00000000u, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{0x40000000u, 0xbf800000u, 0xff800000u, 0x7fc00000u, 0x3f800000u,
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0x80000000u, 0x00000000u, 0x00000000u, 0x80000001u, 0x40800000u,
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0xbf800000u, 0x7f800000u, 0x7fc00000u, 0x3f800000u, 0x80000000u,
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0x00000000u, 0x00000001u, 0x00000000u},
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{O::VMovB32, O::BufferAtomicFMin, O::BufferStoreDword, O::SEndpgm}};
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}
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TestCase BufferAtomicFMinContendedWorkgroup() {
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using O = ShaderOpcode;
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std::vector<u32> code;
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code.push_back(EncodeVop1(0x06, 1, Vgpr(0))); // v_cvt_f32_u32 v1, thread_id.x
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AppendVMovU32(&code, 20, 0);
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AppendBufferStoreOpcode(&code, 0x3f, 1, 20);
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AppendEnd(&code);
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TestCase test;
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test.name = "BufferAtomicFMinContendedWorkgroup";
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test.code = code;
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test.initial = {0x42c80000u}; // 100.0
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test.expected = {0x00000000u}; // min(100.0, 0.0 .. 63.0)
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test.opcodes = {O::VCvtF32U32, O::VMovB32, O::BufferAtomicFMin, O::SEndpgm};
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test.compute_info.threads_num[0] = 64;
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test.compute_info.threads_num[1] = 1;
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test.compute_info.threads_num[2] = 1;
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test.compute_info.thread_ids_num = 1;
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test.has_compute_info = true;
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return test;
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}
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std::vector<u32> MakeRgbaImage(u32 width, u32 height, u32 value = 0) {
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return std::vector<u32>(static_cast<size_t>(width) * height * 4u, value);
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}
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@@ -15279,6 +15367,9 @@ std::vector<TestCase> MakeCases() {
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AddCase(DsSwizzleInvalidSourceLaneZero);
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AddCase(BufferAtomicVariants);
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AddCase(BufferAtomicGlc0DoesNotReturnOldValue);
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AddCase(BufferAtomicFMinExactRawGlcModes);
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AddCase(BufferAtomicFMinSpecialValues);
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AddCase(BufferAtomicFMinContendedWorkgroup);
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AddCase(ImageLoadVariants);
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AddCase(ImageLoadR32UintUsesIntegerSampledImage);
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AddCase(ImageLoad1DUsesScalarCoordinate);
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@@ -4788,6 +4788,8 @@ void TestNewShaderRecompilerAtomicLowering() {
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EncodeMubuf1(5, 0, 1), // buffer_atomic_or
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EncodeMubuf0(0x3b, 40, true, true),
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EncodeMubuf1(6, 0, 1), // buffer_atomic_xor
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0xe0fc0000u,
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0x80010000u, // exact buffer_atomic_fmin v0, s[4:7], 0 (GLC=0)
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EncodeDs0(0x00),
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EncodeDs1(0, 2, 1), // ds_add_u32
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EncodeDs0(0x01),
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@@ -4842,6 +4844,8 @@ void TestNewShaderRecompilerAtomicLowering() {
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"new decoder did not decode buffer atomic signed max");
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Check(Common::ContainsStr(result.decoded_dump, "buffer_atomic_xor"),
|
||||
"new decoder did not decode buffer atomic xor");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "buffer_atomic_fmin"),
|
||||
"new decoder did not decode buffer atomic float min");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "ds_add_u32"),
|
||||
"new decoder did not decode DS atomic add");
|
||||
Check(Common::ContainsStr(result.decoded_dump, "ds_sub_u32"),
|
||||
@@ -4874,6 +4878,8 @@ void TestNewShaderRecompilerAtomicLowering() {
|
||||
"buffer atomic or did not lower to IR");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicXorU32 v6"),
|
||||
"buffer atomic xor did not lower to IR");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicFMinF32 null, v0"),
|
||||
"buffer atomic float min did not lower to IR without a GLC return");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicAddU32 null, v2"),
|
||||
"DS no-return atomic add did not lower to IR");
|
||||
Check(Common::ContainsStr(result.ir_dump, "AtomicSubU32 null, v10"),
|
||||
@@ -4917,6 +4923,8 @@ void TestNewShaderRecompilerAtomicLowering() {
|
||||
Check(SpirvContainsOpcode(result.spirv, 240), "SPIR-V binary does not contain OpAtomicAnd");
|
||||
Check(SpirvContainsOpcode(result.spirv, 241), "SPIR-V binary does not contain OpAtomicOr");
|
||||
Check(SpirvContainsOpcode(result.spirv, 242), "SPIR-V binary does not contain OpAtomicXor");
|
||||
Check(SpirvContainsOpcode(result.spirv, 230),
|
||||
"SPIR-V binary does not contain OpAtomicCompareExchange for float min");
|
||||
Check(SpirvContainsOpcode(result.spirv, 225),
|
||||
"buffer atomic SPIR-V binary does not contain OpMemoryBarrier");
|
||||
CheckSpirvBinaryValidates(result.spirv);
|
||||
|
||||
Reference in New Issue
Block a user