da53bcee60
Add an extra step in GPU initialization to be able to initialize render backends with a valid GPU instance.
275 lines
8.6 KiB
C++
275 lines
8.6 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/engines/const_buffer_engine_interface.h"
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#include "video_core/engines/engine_interface.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/gpu.h"
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#include "video_core/textures/texture.h"
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namespace Core {
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class System;
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}
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namespace Tegra {
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class MemoryManager;
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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/**
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* This Engine is known as GK104_Compute. Documentation can be found in:
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* https://github.com/envytools/envytools/blob/master/rnndb/graph/gk104_compute.xml
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* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h
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*/
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#define KEPLER_COMPUTE_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
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class KeplerCompute final : public ConstBufferEngineInterface, public EngineInterface {
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public:
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explicit KeplerCompute(Core::System& system, MemoryManager& memory_manager);
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~KeplerCompute();
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/// Binds a rasterizer to this engine.
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void BindRasterizer(VideoCore::RasterizerInterface& rasterizer);
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static constexpr std::size_t NumConstBuffers = 8;
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struct Regs {
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static constexpr std::size_t NUM_REGS = 0xCF8;
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union {
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struct {
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INSERT_UNION_PADDING_WORDS(0x60);
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Upload::Registers upload;
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struct {
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union {
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BitField<0, 1, u32> linear;
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};
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} exec_upload;
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u32 data_upload;
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INSERT_UNION_PADDING_WORDS(0x3F);
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struct {
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u32 address;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address) << 8));
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}
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} launch_desc_loc;
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INSERT_UNION_PADDING_WORDS(0x1);
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u32 launch;
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INSERT_UNION_PADDING_WORDS(0x4A7);
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struct {
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u32 address_high;
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u32 address_low;
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u32 limit;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} tsc;
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INSERT_UNION_PADDING_WORDS(0x3);
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struct {
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u32 address_high;
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u32 address_low;
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u32 limit;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} tic;
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INSERT_UNION_PADDING_WORDS(0x22);
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} code_loc;
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INSERT_UNION_PADDING_WORDS(0x3FE);
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u32 tex_cb_index;
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INSERT_UNION_PADDING_WORDS(0x374);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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struct LaunchParams {
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static constexpr std::size_t NUM_LAUNCH_PARAMETERS = 0x40;
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INSERT_PADDING_WORDS(0x8);
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u32 program_start;
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INSERT_PADDING_WORDS(0x2);
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BitField<30, 1, u32> linked_tsc;
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BitField<0, 31, u32> grid_dim_x;
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union {
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BitField<0, 16, u32> grid_dim_y;
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BitField<16, 16, u32> grid_dim_z;
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};
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INSERT_PADDING_WORDS(0x3);
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BitField<0, 18, u32> shared_alloc;
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BitField<16, 16, u32> block_dim_x;
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union {
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BitField<0, 16, u32> block_dim_y;
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BitField<16, 16, u32> block_dim_z;
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};
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union {
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BitField<0, 8, u32> const_buffer_enable_mask;
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BitField<29, 2, u32> cache_layout;
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};
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INSERT_PADDING_WORDS(0x8);
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struct ConstBufferConfig {
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u32 address_low;
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union {
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BitField<0, 8, u32> address_high;
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BitField<15, 17, u32> size;
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};
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high.Value()) << 32) |
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address_low);
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}
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};
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std::array<ConstBufferConfig, NumConstBuffers> const_buffer_config;
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union {
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BitField<0, 20, u32> local_pos_alloc;
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BitField<27, 5, u32> barrier_alloc;
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};
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union {
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BitField<0, 20, u32> local_neg_alloc;
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BitField<24, 5, u32> gpr_alloc;
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};
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union {
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BitField<0, 20, u32> local_crs_alloc;
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BitField<24, 5, u32> sass_version;
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};
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INSERT_PADDING_WORDS(0x10);
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} launch_description{};
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struct {
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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} state{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32),
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"KeplerCompute Regs has wrong size");
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static_assert(sizeof(LaunchParams) == LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32),
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"KeplerCompute LaunchParams has wrong size");
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/// Write the value to the register identified by method.
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void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
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/// Write multiple values to the register identified by method.
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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Texture::FullTextureInfo GetTexture(std::size_t offset) const;
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/// Given a texture handle, returns the TSC and TIC entries.
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Texture::FullTextureInfo GetTextureInfo(Texture::TextureHandle tex_handle) const;
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u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const override;
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SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const override;
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SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const override;
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SamplerDescriptor AccessSampler(u32 handle) const override;
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u32 GetBoundBuffer() const override {
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return regs.tex_cb_index;
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}
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VideoCore::GuestDriverProfile& AccessGuestDriverProfile() override;
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const VideoCore::GuestDriverProfile& AccessGuestDriverProfile() const override;
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private:
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void ProcessLaunch();
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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Core::System& system;
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MemoryManager& memory_manager;
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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Upload::State upload_state;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(KeplerCompute::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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#define ASSERT_LAUNCH_PARAM_POSITION(field_name, position) \
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static_assert(offsetof(KeplerCompute::LaunchParams, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(exec_upload, 0x6C);
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ASSERT_REG_POSITION(data_upload, 0x6D);
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ASSERT_REG_POSITION(launch, 0xAF);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_loc, 0x582);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_LAUNCH_PARAM_POSITION(program_start, 0x8);
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ASSERT_LAUNCH_PARAM_POSITION(grid_dim_x, 0xC);
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ASSERT_LAUNCH_PARAM_POSITION(shared_alloc, 0x11);
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ASSERT_LAUNCH_PARAM_POSITION(block_dim_x, 0x12);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_enable_mask, 0x14);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_config, 0x1D);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Engines
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