Dyncom: Tweak types and log formatting
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				@ -415,7 +415,7 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
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};
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					};
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// clang-format on
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					// clang-format on
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ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
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					ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx) {
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    int n = 0;
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					    int n = 0;
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    int base = 0;
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					    int base = 0;
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    int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
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					    int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
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@ -8,7 +8,7 @@
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enum class ARMDecodeStatus { SUCCESS, FAILURE };
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					enum class ARMDecodeStatus { SUCCESS, FAILURE };
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ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);
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					ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx);
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struct InstructionSetEncodingItem {
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					struct InstructionSetEncodingItem {
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    const char* name;
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					    const char* name;
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@ -5,6 +5,7 @@
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#define CITRA_IGNORE_EXIT(x)
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					#define CITRA_IGNORE_EXIT(x)
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#include <algorithm>
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					#include <algorithm>
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					#include <cinttypes>
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#include <cstdio>
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					#include <cstdio>
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#include "common/common_types.h"
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					#include "common/common_types.h"
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#include "common/logging/log.h"
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					#include "common/logging/log.h"
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@ -808,8 +809,8 @@ MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
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static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
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					static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
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                                                    ARM_INST_PTR& inst_base) {
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					                                                    ARM_INST_PTR& inst_base) {
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    unsigned int inst_size = 4;
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					    u32 inst_size = 4;
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    unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
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					    u32 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
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    // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
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					    // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
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    // instruction
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					    // instruction
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@ -828,10 +829,11 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
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    int idx;
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					    int idx;
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    if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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					    if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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        std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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					        std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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        LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr,
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					        LOG_ERROR(Core_ARM11,
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                  disasm.c_str(), inst);
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					                  "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %s [%08" PRIX32 "]",
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        LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag,
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					                  phys_addr, disasm.c_str(), inst);
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                  cpu->Reg[15]);
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					        LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
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					                  cpu->TFlag, cpu->Reg[15]);
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        CITRA_IGNORE_EXIT(-1);
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					        CITRA_IGNORE_EXIT(-1);
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    }
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					    }
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    inst_base = arm_instruction_trans[idx](inst, idx);
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					    inst_base = arm_instruction_trans[idx](inst, idx);
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