gl_rasterizer_cache: Use zeta_width and zeta_height registers for depth buffer.
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@ -65,8 +65,8 @@ struct FormatTuple {
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return params;
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return params;
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}
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config, Tegra::GPUVAddr zeta_address,
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Tegra::GPUVAddr zeta_address,
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Tegra::DepthFormat format) {
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Tegra::DepthFormat format) {
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SurfaceParams params{};
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SurfaceParams params{};
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@ -77,9 +77,9 @@ struct FormatTuple {
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.type = GetFormatType(params.pixel_format);
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params.type = GetFormatType(params.pixel_format);
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params.size_in_bytes = params.SizeInBytes();
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params.size_in_bytes = params.SizeInBytes();
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params.width = config.width;
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params.width = zeta_width;
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params.height = config.height;
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params.height = zeta_height;
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params.unaligned_height = config.height;
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params.unaligned_height = zeta_height;
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params.size_in_bytes = params.SizeInBytes();
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params.size_in_bytes = params.SizeInBytes();
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return params;
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return params;
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}
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}
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@ -519,8 +519,8 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
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}
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}
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if (using_depth_fb) {
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if (using_depth_fb) {
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depth_params =
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depth_params = SurfaceParams::CreateForDepthBuffer(regs.zeta_width, regs.zeta_height,
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SurfaceParams::CreateForDepthBuffer(regs.rt[0], regs.zeta.Address(), regs.zeta.format);
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regs.zeta.Address(), regs.zeta.format);
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}
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}
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MathUtil::Rectangle<u32> color_rect{};
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MathUtil::Rectangle<u32> color_rect{};
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@ -365,9 +365,9 @@ struct SurfaceParams {
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config);
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config);
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/// Creates SurfaceParams for a depth buffer configuration
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/// Creates SurfaceParams for a depth buffer configuration
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static SurfaceParams CreateForDepthBuffer(
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static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config,
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Tegra::GPUVAddr zeta_address,
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Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format);
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Tegra::DepthFormat format);
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Tegra::GPUVAddr addr;
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Tegra::GPUVAddr addr;
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bool is_tiled;
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bool is_tiled;
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