Merge pull request #869 from Subv/ubsan
Corrected a few error cases detected by asan/ubsan
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						3575c076cb
					
				@ -97,7 +97,9 @@ u32 nvhost_ctrl_gpu::GetTPCMasks(const std::vector<u8>& input, std::vector<u8>&
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u32 nvhost_ctrl_gpu::GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output) {
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    LOG_DEBUG(Service_NVDRV, "called");
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    IoctlActiveSlotMask params{};
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    std::memcpy(¶ms, input.data(), input.size());
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    if (input.size() > 0) {
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        std::memcpy(¶ms, input.data(), input.size());
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    }
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    params.slot = 0x07;
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    params.mask = 0x01;
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    std::memcpy(output.data(), ¶ms, output.size());
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@ -107,7 +109,9 @@ u32 nvhost_ctrl_gpu::GetActiveSlotMask(const std::vector<u8>& input, std::vector
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u32 nvhost_ctrl_gpu::ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output) {
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    LOG_DEBUG(Service_NVDRV, "called");
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    IoctlZcullGetCtxSize params{};
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    std::memcpy(¶ms, input.data(), input.size());
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    if (input.size() > 0) {
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        std::memcpy(¶ms, input.data(), input.size());
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    }
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    params.size = 0x1;
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    std::memcpy(output.data(), ¶ms, output.size());
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    return 0;
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@ -116,7 +120,11 @@ u32 nvhost_ctrl_gpu::ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u
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u32 nvhost_ctrl_gpu::ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output) {
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    LOG_DEBUG(Service_NVDRV, "called");
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    IoctlNvgpuGpuZcullGetInfoArgs params{};
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    std::memcpy(¶ms, input.data(), input.size());
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    if (input.size() > 0) {
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        std::memcpy(¶ms, input.data(), input.size());
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    }
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    params.width_align_pixels = 0x20;
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    params.height_align_pixels = 0x20;
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    params.pixel_squares_by_aliquots = 0x400;
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@ -132,9 +132,12 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
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    LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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                params.address, params.num_entries, params.flags);
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    auto entries = std::vector<IoctlGpfifoEntry>();
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    entries.resize(params.num_entries);
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    std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)],
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    ASSERT_MSG(input.size() ==
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                   sizeof(IoctlSubmitGpfifo) + params.num_entries * sizeof(IoctlGpfifoEntry),
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               "Incorrect input size");
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    std::vector<IoctlGpfifoEntry> entries(params.num_entries);
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    std::memcpy(entries.data(), &input[sizeof(IoctlSubmitGpfifo)],
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                params.num_entries * sizeof(IoctlGpfifoEntry));
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    for (auto entry : entries) {
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        Tegra::GPUVAddr va_addr = entry.Address();
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@ -102,11 +102,11 @@ bool MacroInterpreter::Step(const std::vector<u32>& code, bool is_delay_slot) {
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        if (taken) {
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            // Ignore the delay slot if the branch has the annul bit.
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            if (opcode.branch_annul) {
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                pc = base_address + (opcode.immediate << 2);
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                pc = base_address + opcode.GetBranchTarget();
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                return true;
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            }
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            delayed_pc = base_address + (opcode.immediate << 2);
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            delayed_pc = base_address + opcode.GetBranchTarget();
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            // Execute one more instruction due to the delay slot.
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            return Step(code, true);
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        }
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@ -91,6 +91,10 @@ private:
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        u32 GetBitfieldMask() const {
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            return (1 << bf_size) - 1;
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        }
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        s32 GetBranchTarget() const {
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            return static_cast<s32>(immediate * sizeof(u32));
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        }
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    };
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    union MethodAddress {
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