VideoCore: Consistently use shader configuration to load attributes
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				@ -511,7 +511,7 @@ void GraphicsVertexShaderWidget::Reload(bool replace_vertex_data, void* vertex_d
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    auto& shader_config = Pica::g_state.regs.vs;
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    for (auto instr : shader_setup.program_code)
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        info.code.push_back({instr});
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    int num_attributes = Pica::g_state.regs.vertex_attributes.GetNumTotalAttributes();
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    int num_attributes = shader_config.max_input_attribute_index + 1;
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    for (auto pattern : shader_setup.swizzle_data)
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        info.swizzle_info.push_back({pattern});
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@ -522,11 +522,11 @@ void GraphicsVertexShaderWidget::Reload(bool replace_vertex_data, void* vertex_d
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    // Generate debug information
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    Pica::Shader::InterpreterEngine shader_engine;
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    shader_engine.SetupBatch(shader_setup, entry_point);
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    debug_data = shader_engine.ProduceDebugInfo(shader_setup, input_vertex, num_attributes);
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    debug_data = shader_engine.ProduceDebugInfo(shader_setup, input_vertex, shader_config);
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    // Reload widget state
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    for (int attr = 0; attr < num_attributes; ++attr) {
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        unsigned source_attr = shader_config.input_register_map.GetRegisterForAttribute(attr);
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        unsigned source_attr = shader_config.GetRegisterForAttribute(attr);
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        input_data_mapping[attr]->setText(QString("-> v%1").arg(source_attr));
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        input_data_container[attr]->setVisible(true);
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    }
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@ -151,7 +151,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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                        g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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                                                 static_cast<void*>(&immediate_input));
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                    Shader::UnitState shader_unit;
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                    shader_unit.LoadInput(immediate_input, regs.vs.max_input_attribute_index + 1);
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                    shader_unit.LoadInput(regs.vs, immediate_input);
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                    shader_engine->Run(g_state.vs, shader_unit);
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                    auto output_vertex = Shader::OutputVertex::FromRegisters(
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                        shader_unit.registers.output, regs, regs.vs.output_mask);
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@ -288,7 +288,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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                if (g_debug_context)
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                    g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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                                             (void*)&input);
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                shader_unit.LoadInput(input, loader.GetNumTotalAttributes());
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                shader_unit.LoadInput(regs.vs, input);
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                shader_engine->Run(g_state.vs, shader_unit);
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                // Retrieve vertex from register data
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@ -1225,36 +1225,15 @@ struct Regs {
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        // Offset to shader program entry point (in words)
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        BitField<0, 16, u32> main_offset;
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        union {
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            BitField<0, 4, u64> attribute0_register;
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            BitField<4, 4, u64> attribute1_register;
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            BitField<8, 4, u64> attribute2_register;
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            BitField<12, 4, u64> attribute3_register;
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            BitField<16, 4, u64> attribute4_register;
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            BitField<20, 4, u64> attribute5_register;
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            BitField<24, 4, u64> attribute6_register;
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            BitField<28, 4, u64> attribute7_register;
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            BitField<32, 4, u64> attribute8_register;
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            BitField<36, 4, u64> attribute9_register;
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            BitField<40, 4, u64> attribute10_register;
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            BitField<44, 4, u64> attribute11_register;
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            BitField<48, 4, u64> attribute12_register;
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            BitField<52, 4, u64> attribute13_register;
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            BitField<56, 4, u64> attribute14_register;
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            BitField<60, 4, u64> attribute15_register;
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        /// Maps input attributes to registers. 4-bits per attribute, specifying a register index
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        u32 input_attribute_to_register_map_low;
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        u32 input_attribute_to_register_map_high;
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            int GetRegisterForAttribute(int attribute_index) const {
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                u64 fields[] = {
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                    attribute0_register,  attribute1_register,  attribute2_register,
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                    attribute3_register,  attribute4_register,  attribute5_register,
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                    attribute6_register,  attribute7_register,  attribute8_register,
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                    attribute9_register,  attribute10_register, attribute11_register,
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                    attribute12_register, attribute13_register, attribute14_register,
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                    attribute15_register,
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                };
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                return (int)fields[attribute_index];
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            }
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        } input_register_map;
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        unsigned int GetRegisterForAttribute(unsigned int attribute_index) const {
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            u64 map = ((u64)input_attribute_to_register_map_high << 32) |
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                      (u64)input_attribute_to_register_map_low;
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            return (map >> (attribute_index * 4)) & 0b1111;
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        }
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        BitField<0, 16, u32> output_mask;
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@ -71,12 +71,13 @@ OutputVertex OutputVertex::FromRegisters(Math::Vec4<float24> output_regs[16], co
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    return ret;
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}
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void UnitState::LoadInput(const AttributeBuffer& input, int num_attributes) {
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    // Setup input register table
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    const auto& attribute_register_map = g_state.regs.vs.input_register_map;
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void UnitState::LoadInput(const Regs::ShaderConfig& config, const AttributeBuffer& input) {
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    const unsigned max_attribute = config.max_input_attribute_index;
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    for (int i = 0; i < num_attributes; i++)
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        registers.input[attribute_register_map.GetRegisterForAttribute(i)] = input.attr[i];
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    for (unsigned attr = 0; attr <= max_attribute; ++attr) {
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        unsigned reg = config.GetRegisterForAttribute(attr);
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        registers.input[reg] = input.attr[attr];
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    }
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}
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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@ -137,10 +137,10 @@ struct UnitState {
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    /**
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     * Loads the unit state with an input vertex.
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     *
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     * @param input Input vertex into the shader
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     * @param num_attributes The number of vertex shader attributes to load
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     * @param config Shader configuration registers corresponding to the unit.
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     * @param input Attribute buffer to load into the input registers.
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     */
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    void LoadInput(const AttributeBuffer& input, int num_attributes);
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    void LoadInput(const Regs::ShaderConfig& config, const AttributeBuffer& input);
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};
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struct ShaderSetup {
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@ -669,13 +669,13 @@ void InterpreterEngine::Run(const ShaderSetup& setup, UnitState& state) const {
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DebugData<true> InterpreterEngine::ProduceDebugInfo(const ShaderSetup& setup,
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                                                    const AttributeBuffer& input,
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                                                    int num_attributes) const {
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                                                    const Regs::ShaderConfig& config) const {
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    UnitState state;
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    DebugData<true> debug_data;
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    // Setup input register table
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    boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero()));
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    state.LoadInput(input, num_attributes);
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    state.LoadInput(config, input);
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    RunInterpreter(setup, state, debug_data, setup.engine_data.entry_point);
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    return debug_data;
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}
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@ -19,12 +19,11 @@ public:
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    /**
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     * Produce debug information based on the given shader and input vertex
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     * @param input Input vertex into the shader
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     * @param num_attributes The number of vertex shader attributes
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     * @param config Configuration object for the shader pipeline
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     * @return Debug information for this shader with regards to the given vertex
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     */
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    DebugData<true> ProduceDebugInfo(const ShaderSetup& setup, const AttributeBuffer& input,
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                                     int num_attributes) const;
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                                     const Regs::ShaderConfig& config) const;
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};
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} // namespace
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