incdir  "tests"
include "dsp_base.inc"

test_main:

; Test parameters
lri $AC0.M, #0x0000 ; start
lri $AC0.L, #0x0000 ; start
lri $AC1.M, #0x0000 ; end
lri $AC1.L, #0x0011 ; end

; Set the sample format
lri $AC0.H, #0x0
sr @FORMAT, $AC0.H
; Set the starting and current address
srs @ACSAH, $AC0.M
srs @ACCAH, $AC0.M
srs @ACSAL, $AC0.L
srs @ACCAL, $AC0.L
; Set the ending address
srs @ACEAH, $AC1.M
srs @ACEAL, $AC1.L

; Reset some registers (these must be reset after setting FORMAT)
lri $AC0.H, #0xffff
sr @PRED_SCALE, $AC0.H
sr @YN1, $AC0.H
sr @YN2, $AC0.H

call load_hw_reg_to_regs
call send_back ; check the accelerator regs before a read

bloopi #40, end_of_loop
  lr $IX3, @ACDSAMP
  call load_hw_reg_to_regs
  call send_back ; after a read
  nop ; Loops that end at a return of a call are buggy on hw
end_of_loop:
  nop

jmp end_of_test

load_hw_reg_to_regs:
  lr $AR0, @FORMAT
  lr $AR1, @0xffd2 ; unknown
  lr $AR2, @PRED_SCALE
  lr $AR3, @YN1
  lr $IX0, @YN2
  lr $IX1, @ACIN

  lri $AC0.H, #0
  lrs $AC0.M, @ACSAH
  lrs $AC0.L, @ACSAL

  lri $AC1.H, #0
  lrs $AC1.M, @ACEAH
  lrs $AC1.L, @ACEAL

  lrs $AX0.H, @ACCAH
  lrs $AX0.L, @ACCAL
  lrs $AX1.H, @ACCAH
  lrs $AX1.L, @ACCAL

  lrs $AX1.H, @ACCAH
  lrs $AX1.L, @ACCAL

  ret