632 lines
27 KiB
C++
632 lines
27 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <numeric>
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#include <nihstro/shader_bytecode.h>
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#include "common/file_util.h"
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#include "video_core/pica.h"
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#include "video_core/pica_state.h"
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#include "video_core/shader/shader.h"
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#include "video_core/shader/shader_interpreter.h"
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using nihstro::OpCode;
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using nihstro::Instruction;
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::SwizzlePattern;
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namespace Pica {
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namespace Shader {
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template<bool Debug>
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void RunInterpreter(UnitState<Debug>& state) {
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const auto& uniforms = g_state.vs.uniforms;
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const auto& swizzle_data = g_state.vs.swizzle_data;
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const auto& program_code = g_state.vs.program_code;
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// Placeholder for invalid inputs
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static float24 dummy_vec4_float24[4];
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unsigned iteration = 0;
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bool exit_loop = false;
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while (!exit_loop) {
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if (!state.call_stack.empty()) {
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auto& top = state.call_stack.back();
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if (state.program_counter == top.final_address) {
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state.address_registers[2] += top.loop_increment;
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if (top.repeat_counter-- == 0) {
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state.program_counter = top.return_address;
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state.call_stack.pop_back();
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} else {
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state.program_counter = top.loop_address;
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}
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// TODO: Is "trying again" accurate to hardware?
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continue;
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}
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}
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const Instruction instr = { program_code[state.program_counter] };
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const SwizzlePattern swizzle = { swizzle_data[instr.common.operand_desc_id] };
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static auto call = [](UnitState<Debug>& state, u32 offset, u32 num_instructions,
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u32 return_offset, u8 repeat_count, u8 loop_increment) {
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state.program_counter = offset - 1; // -1 to make sure when incrementing the PC we end up at the correct offset
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ASSERT(state.call_stack.size() < state.call_stack.capacity());
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state.call_stack.push_back({ offset + num_instructions, return_offset, repeat_count, loop_increment, offset });
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};
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Record<DebugDataRecord::CUR_INSTR>(state.debug, iteration, state.program_counter);
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if (iteration > 0)
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Record<DebugDataRecord::NEXT_INSTR>(state.debug, iteration - 1, state.program_counter);
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + state.program_counter);
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auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
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switch (source_reg.GetRegisterType()) {
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case RegisterType::Input:
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return &state.registers.input[source_reg.GetIndex()].x;
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case RegisterType::Temporary:
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return &state.registers.temporary[source_reg.GetIndex()].x;
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case RegisterType::FloatUniform:
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return &uniforms.f[source_reg.GetIndex()].x;
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default:
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return dummy_vec4_float24;
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}
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};
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switch (instr.opcode.Value().GetInfo().type) {
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case OpCode::Type::Arithmetic:
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{
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const bool is_inverted = (0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed));
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const int address_offset = (instr.common.address_register_index == 0)
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? 0 : state.address_registers[instr.common.address_register_index - 1];
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const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted) + (!is_inverted * address_offset));
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const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted) + ( is_inverted * address_offset));
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const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
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const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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if (negate_src1) {
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src1[0] = src1[0] * float24::FromFloat32(-1);
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src1[1] = src1[1] * float24::FromFloat32(-1);
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src1[2] = src1[2] * float24::FromFloat32(-1);
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src1[3] = src1[3] * float24::FromFloat32(-1);
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}
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float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(2)],
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src2_[(int)swizzle.GetSelectorSrc2(3)],
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};
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if (negate_src2) {
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src2[0] = src2[0] * float24::FromFloat32(-1);
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src2[1] = src2[1] * float24::FromFloat32(-1);
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src2[2] = src2[2] * float24::FromFloat32(-1);
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.common.dest.Value() < 0x10) ? &state.registers.output[instr.common.dest.Value().GetIndex()][0]
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: (instr.common.dest.Value() < 0x20) ? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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switch (instr.opcode.Value().EffectiveOpCode()) {
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case OpCode::Id::ADD:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] + src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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case OpCode::Id::MUL:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] * src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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case OpCode::Id::FLR:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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case OpCode::Id::MAX:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// NOTE: Exact form required to match NaN semantics to hardware:
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// max(0, NaN) -> NaN
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// max(NaN, 0) -> 0
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dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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case OpCode::Id::MIN:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// NOTE: Exact form required to match NaN semantics to hardware:
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// min(0, NaN) -> NaN
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// min(NaN, 0) -> 0
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dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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case OpCode::Id::DP3:
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case OpCode::Id::DP4:
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case OpCode::Id::DPH:
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case OpCode::Id::DPHI:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
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if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
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src1[3] = float24::FromFloat32(1.0f);
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int num_components = (opcode == OpCode::Id::DP3) ? 3 : 4;
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float24 dot = std::inner_product(src1, src1 + num_components, src2, float24::FromFloat32(0.f));
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = dot;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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// Reciprocal
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case OpCode::Id::RCP:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = rcp_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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// Reciprocal Square Root
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case OpCode::Id::RSQ:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = rsq_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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case OpCode::Id::MOVA:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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for (int i = 0; i < 2; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Figure out how the rounding is done on hardware
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state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
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}
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Record<DebugDataRecord::ADDR_REG_OUT>(state.debug, iteration, state.address_registers);
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break;
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}
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case OpCode::Id::MOV:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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case OpCode::Id::SGE:
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case OpCode::Id::SGEI:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f) : float24::FromFloat32(0.0f);
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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case OpCode::Id::SLT:
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case OpCode::Id::SLTI:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f) : float24::FromFloat32(0.0f);
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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case OpCode::Id::CMP:
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
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for (int i = 0; i < 2; ++i) {
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// TODO: Can you restrict to one compare via dest masking?
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auto compare_op = instr.common.compare_op;
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auto op = (i == 0) ? compare_op.x.Value() : compare_op.y.Value();
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switch (op) {
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case Instruction::Common::CompareOpType::Equal:
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state.conditional_code[i] = (src1[i] == src2[i]);
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break;
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case Instruction::Common::CompareOpType::NotEqual:
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state.conditional_code[i] = (src1[i] != src2[i]);
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break;
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case Instruction::Common::CompareOpType::LessThan:
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state.conditional_code[i] = (src1[i] < src2[i]);
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break;
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case Instruction::Common::CompareOpType::LessEqual:
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state.conditional_code[i] = (src1[i] <= src2[i]);
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break;
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case Instruction::Common::CompareOpType::GreaterThan:
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state.conditional_code[i] = (src1[i] > src2[i]);
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break;
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case Instruction::Common::CompareOpType::GreaterEqual:
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state.conditional_code[i] = (src1[i] >= src2[i]);
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break;
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default:
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LOG_ERROR(HW_GPU, "Unknown compare mode %x", static_cast<int>(op));
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break;
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}
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}
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Record<DebugDataRecord::CMP_RESULT>(state.debug, iteration, state.conditional_code);
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break;
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case OpCode::Id::EX2:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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// EX2 only takes first component exp2 and writes it to all dest components
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float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = ex2_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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case OpCode::Id::LG2:
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{
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Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
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Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
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// LG2 only takes the first component log2 and writes it to all dest components
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float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = lg2_res;
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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}
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default:
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LOG_ERROR(HW_GPU, "Unhandled arithmetic instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
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DEBUG_ASSERT(false);
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break;
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}
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break;
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}
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case OpCode::Type::MultiplyAdd:
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{
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if ((instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD) ||
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(instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI)) {
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const SwizzlePattern& swizzle = *reinterpret_cast<const SwizzlePattern*>(&swizzle_data[instr.mad.operand_desc_id]);
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bool is_inverted = (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI);
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const int address_offset = (instr.mad.address_register_index == 0)
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? 0 : state.address_registers[instr.mad.address_register_index - 1];
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const float24* src1_ = LookupSourceRegister(instr.mad.GetSrc1(is_inverted));
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const float24* src2_ = LookupSourceRegister(instr.mad.GetSrc2(is_inverted) + (!is_inverted * address_offset));
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const float24* src3_ = LookupSourceRegister(instr.mad.GetSrc3(is_inverted) + ( is_inverted * address_offset));
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const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
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const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
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const bool negate_src3 = ((bool)swizzle.negate_src3 != false);
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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if (negate_src1) {
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src1[0] = src1[0] * float24::FromFloat32(-1);
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src1[1] = src1[1] * float24::FromFloat32(-1);
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src1[2] = src1[2] * float24::FromFloat32(-1);
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src1[3] = src1[3] * float24::FromFloat32(-1);
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}
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float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(2)],
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src2_[(int)swizzle.GetSelectorSrc2(3)],
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};
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if (negate_src2) {
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src2[0] = src2[0] * float24::FromFloat32(-1);
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src2[1] = src2[1] * float24::FromFloat32(-1);
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src2[2] = src2[2] * float24::FromFloat32(-1);
|
|
src2[3] = src2[3] * float24::FromFloat32(-1);
|
|
}
|
|
float24 src3[4] = {
|
|
src3_[(int)swizzle.GetSelectorSrc3(0)],
|
|
src3_[(int)swizzle.GetSelectorSrc3(1)],
|
|
src3_[(int)swizzle.GetSelectorSrc3(2)],
|
|
src3_[(int)swizzle.GetSelectorSrc3(3)],
|
|
};
|
|
if (negate_src3) {
|
|
src3[0] = src3[0] * float24::FromFloat32(-1);
|
|
src3[1] = src3[1] * float24::FromFloat32(-1);
|
|
src3[2] = src3[2] * float24::FromFloat32(-1);
|
|
src3[3] = src3[3] * float24::FromFloat32(-1);
|
|
}
|
|
|
|
float24* dest = (instr.mad.dest.Value() < 0x10) ? &state.registers.output[instr.mad.dest.Value().GetIndex()][0]
|
|
: (instr.mad.dest.Value() < 0x20) ? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
|
|
: dummy_vec4_float24;
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
Record<DebugDataRecord::SRC3>(state.debug, iteration, src3);
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
for (int i = 0; i < 4; ++i) {
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
continue;
|
|
|
|
dest[i] = src1[i] * src2[i] + src3[i];
|
|
}
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
} else {
|
|
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
|
|
(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
|
|
}
|
|
break;
|
|
}
|
|
|
|
default:
|
|
{
|
|
static auto evaluate_condition = [](const UnitState<Debug>& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
|
|
bool results[2] = { refx == state.conditional_code[0],
|
|
refy == state.conditional_code[1] };
|
|
|
|
switch (flow_control.op) {
|
|
case flow_control.Or:
|
|
return results[0] || results[1];
|
|
|
|
case flow_control.And:
|
|
return results[0] && results[1];
|
|
|
|
case flow_control.JustX:
|
|
return results[0];
|
|
|
|
case flow_control.JustY:
|
|
return results[1];
|
|
}
|
|
};
|
|
|
|
// Handle each instruction on its own
|
|
switch (instr.opcode.Value()) {
|
|
case OpCode::Id::END:
|
|
exit_loop = true;
|
|
break;
|
|
|
|
case OpCode::Id::JMPC:
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, state.conditional_code);
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
|
state.program_counter = instr.flow_control.dest_offset - 1;
|
|
}
|
|
break;
|
|
|
|
case OpCode::Id::JMPU:
|
|
Record<DebugDataRecord::COND_BOOL_IN>(state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id] == !(instr.flow_control.num_instructions & 1)) {
|
|
state.program_counter = instr.flow_control.dest_offset - 1;
|
|
}
|
|
break;
|
|
|
|
case OpCode::Id::CALL:
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
state.program_counter + 1, 0, 0);
|
|
break;
|
|
|
|
case OpCode::Id::CALLU:
|
|
Record<DebugDataRecord::COND_BOOL_IN>(state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
state.program_counter + 1, 0, 0);
|
|
}
|
|
break;
|
|
|
|
case OpCode::Id::CALLC:
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, state.conditional_code);
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
state.program_counter + 1, 0, 0);
|
|
}
|
|
break;
|
|
|
|
case OpCode::Id::NOP:
|
|
break;
|
|
|
|
case OpCode::Id::IFU:
|
|
Record<DebugDataRecord::COND_BOOL_IN>(state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
|
call(state,
|
|
state.program_counter + 1,
|
|
instr.flow_control.dest_offset - state.program_counter - 1,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
|
} else {
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
|
}
|
|
|
|
break;
|
|
|
|
case OpCode::Id::IFC:
|
|
{
|
|
// TODO: Do we need to consider swizzlers here?
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, state.conditional_code);
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
|
call(state,
|
|
state.program_counter + 1,
|
|
instr.flow_control.dest_offset - state.program_counter - 1,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
|
} else {
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
case OpCode::Id::LOOP:
|
|
{
|
|
Math::Vec4<u8> loop_param(uniforms.i[instr.flow_control.int_uniform_id].x,
|
|
uniforms.i[instr.flow_control.int_uniform_id].y,
|
|
uniforms.i[instr.flow_control.int_uniform_id].z,
|
|
uniforms.i[instr.flow_control.int_uniform_id].w);
|
|
state.address_registers[2] = loop_param.y;
|
|
|
|
Record<DebugDataRecord::LOOP_INT_IN>(state.debug, iteration, loop_param);
|
|
call(state,
|
|
state.program_counter + 1,
|
|
instr.flow_control.dest_offset - state.program_counter + 1,
|
|
instr.flow_control.dest_offset + 1,
|
|
loop_param.x,
|
|
loop_param.z);
|
|
break;
|
|
}
|
|
|
|
default:
|
|
LOG_ERROR(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
|
|
(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
++state.program_counter;
|
|
++iteration;
|
|
}
|
|
}
|
|
|
|
// Explicit instantiation
|
|
template void RunInterpreter(UnitState<false>& state);
|
|
template void RunInterpreter(UnitState<true>& state);
|
|
|
|
} // namespace
|
|
|
|
} // namespace
|