987a170665
Only tiled->linear and linear->tiled copies that aren't offsetted are supported for now. Queries are not supported. Swizzled copies are not supported.
156 lines
4.3 KiB
C++
156 lines
4.3 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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class MaxwellDMA final {
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public:
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explicit MaxwellDMA(MemoryManager& memory_manager);
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~MaxwellDMA() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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struct Regs {
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static constexpr size_t NUM_REGS = 0x1D6;
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struct Parameters {
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union {
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BitField<0, 4, u32> block_depth;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_width;
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};
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u32 size_x;
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u32 size_y;
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u32 size_z;
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u32 pos_z;
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union {
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BitField<0, 16, u32> pos_x;
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BitField<16, 16, u32> pos_y;
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};
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u32 BlockHeight() const {
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return 1 << block_height;
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}
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};
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static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
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enum class CopyMode : u32 {
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None = 0,
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Unk1 = 1,
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Unk2 = 2,
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};
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enum class QueryMode : u32 {
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None = 0,
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Short = 1,
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Long = 2,
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};
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enum class QueryIntr : u32 {
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None = 0,
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Block = 1,
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NonBlock = 2,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0xC0);
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struct {
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union {
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BitField<0, 2, CopyMode> copy_mode;
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BitField<2, 1, u32> flush;
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BitField<3, 2, QueryMode> query_mode;
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BitField<5, 2, QueryIntr> query_intr;
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BitField<7, 1, u32> is_src_linear;
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BitField<8, 1, u32> is_dst_linear;
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BitField<9, 1, u32> enable_2d;
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BitField<10, 1, u32> enable_swizzle;
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};
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} exec;
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INSERT_PADDING_WORDS(0x3F);
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} src_address;
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} dst_address;
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u32 src_pitch;
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u32 dst_pitch;
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u32 x_count;
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u32 y_count;
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INSERT_PADDING_WORDS(0xBB);
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Parameters dst_params;
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INSERT_PADDING_WORDS(1);
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Parameters src_params;
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INSERT_PADDING_WORDS(0x13);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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MemoryManager& memory_manager;
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private:
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/// Performs the copy from the source buffer to the destination buffer as configured in the
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/// registers.
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void HandleCopy();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(exec, 0xC0);
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ASSERT_REG_POSITION(src_address, 0x100);
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ASSERT_REG_POSITION(dst_address, 0x102);
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ASSERT_REG_POSITION(src_pitch, 0x104);
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ASSERT_REG_POSITION(dst_pitch, 0x105);
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ASSERT_REG_POSITION(x_count, 0x106);
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ASSERT_REG_POSITION(y_count, 0x107);
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ASSERT_REG_POSITION(dst_params, 0x1C3);
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ASSERT_REG_POSITION(src_params, 0x1CA);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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