638 lines
20 KiB
C++
638 lines
20 KiB
C++
/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "common/logging/log.h"
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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// Unsigned sum of absolute difference
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u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
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{
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if (left > right)
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return left - right;
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return right - left;
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}
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// Add with carry, indicates if a carry-out or signed overflow occurred.
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u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bool* overflow_occurred)
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{
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u64 unsigned_sum = (u64)left + (u64)right + (u64)carry_in;
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s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)carry_in;
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u64 result = (unsigned_sum & 0xFFFFFFFF);
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if (carry_out_occurred)
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*carry_out_occurred = (result != unsigned_sum);
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if (overflow_occurred)
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*overflow_occurred = ((s64)(s32)result != signed_sum);
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return (u32)result;
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}
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// Compute whether an addition of A and B, giving RESULT, overflowed.
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bool AddOverflow(ARMword a, ARMword b, ARMword result)
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{
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return ((NEG(a) && NEG(b) && POS(result)) ||
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(POS(a) && POS(b) && NEG(result)));
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}
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// Compute whether a subtraction of A and B, giving RESULT, overflowed.
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bool SubOverflow(ARMword a, ARMword b, ARMword result)
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{
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return ((NEG(a) && POS(b) && POS(result)) ||
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(POS(a) && NEG(b) && NEG(result)));
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}
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// Returns true if the Q flag should be set as a result of overflow.
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bool ARMul_AddOverflowQ(ARMword a, ARMword b)
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{
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u32 result = a + b;
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if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)
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return true;
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return false;
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}
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// 8-bit signed saturated addition
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u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right)
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{
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u8 result = left + right;
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if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) == 0) {
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if (left & 0x80)
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result = 0x80;
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else
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result = 0x7F;
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}
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return result;
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}
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// 8-bit signed saturated subtraction
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u8 ARMul_SignedSaturatedSub8(u8 left, u8 right)
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{
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u8 result = left - right;
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if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) != 0) {
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if (left & 0x80)
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result = 0x80;
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else
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result = 0x7F;
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}
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return result;
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}
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// 16-bit signed saturated addition
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u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right)
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{
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u16 result = left + right;
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if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) == 0) {
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if (left & 0x8000)
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result = 0x8000;
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else
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result = 0x7FFF;
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}
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return result;
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}
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// 16-bit signed saturated subtraction
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u16 ARMul_SignedSaturatedSub16(u16 left, u16 right)
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{
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u16 result = left - right;
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if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) != 0) {
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if (left & 0x8000)
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result = 0x8000;
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else
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result = 0x7FFF;
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}
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return result;
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}
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// 8-bit unsigned saturated addition
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u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right)
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{
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u8 result = left + right;
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if (result < left)
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result = 0xFF;
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return result;
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}
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// 16-bit unsigned saturated addition
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u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right)
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{
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u16 result = left + right;
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if (result < left)
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result = 0xFFFF;
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return result;
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}
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// 8-bit unsigned saturated subtraction
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u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right)
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{
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if (left <= right)
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return 0;
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return left - right;
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}
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// 16-bit unsigned saturated subtraction
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u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right)
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{
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if (left <= right)
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return 0;
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return left - right;
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}
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// Signed saturation.
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u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred)
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{
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const u32 max = (1 << shift) - 1;
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const s32 top = (value >> shift);
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if (top > 0) {
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*saturation_occurred = true;
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return max;
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}
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else if (top < -1) {
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*saturation_occurred = true;
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return ~max;
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}
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*saturation_occurred = false;
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return (u32)value;
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}
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// Unsigned saturation
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u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred)
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{
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const u32 max = (1 << shift) - 1;
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if (value < 0) {
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*saturation_occurred = true;
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return 0;
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} else if ((u32)value > max) {
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*saturation_occurred = true;
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return max;
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}
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*saturation_occurred = false;
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return (u32)value;
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}
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// Whether or not the given CPU is in big endian mode (E bit is set)
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bool InBigEndianMode(ARMul_State* cpu)
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{
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return (cpu->Cpsr & (1 << 9)) != 0;
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}
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// Whether or not the given CPU is in a mode other than user mode.
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bool InAPrivilegedMode(ARMul_State* cpu)
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{
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return (cpu->Mode != USER32MODE);
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}
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// Reads from the CP15 registers. Used with implementation of the MRC instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
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{
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// Unprivileged registers
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if (crn == 13 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 2)
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return cpu->CP15[CP15_THREAD_UPRW];
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if (opcode_2 == 3)
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return cpu->CP15[CP15_THREAD_URO];
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}
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if (InAPrivilegedMode(cpu))
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{
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if (crn == 0 && opcode_1 == 0)
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{
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if (crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_MAIN_ID];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_CACHE_TYPE];
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if (opcode_2 == 3)
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return cpu->CP15[CP15_TLB_TYPE];
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if (opcode_2 == 5)
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return cpu->CP15[CP15_CPU_ID];
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}
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else if (crm == 1)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_PROCESSOR_FEATURE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_PROCESSOR_FEATURE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15_DEBUG_FEATURE_0];
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if (opcode_2 == 4)
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0];
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if (opcode_2 == 5)
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1];
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if (opcode_2 == 6)
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2];
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if (opcode_2 == 7)
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3];
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}
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else if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_ISA_FEATURE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_ISA_FEATURE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15_ISA_FEATURE_2];
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if (opcode_2 == 3)
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return cpu->CP15[CP15_ISA_FEATURE_3];
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if (opcode_2 == 4)
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return cpu->CP15[CP15_ISA_FEATURE_4];
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}
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}
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_CONTROL];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_AUXILIARY_CONTROL];
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if (opcode_2 == 2)
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return cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL];
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}
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if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15_TRANSLATION_BASE_CONTROL];
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}
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if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL];
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if (crn == 5 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_FAULT_STATUS];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_INSTR_FAULT_STATUS];
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}
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if (crn == 6 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_FAULT_ADDRESS];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_WFAR];
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}
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if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
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return cpu->CP15[CP15_PHYS_ADDRESS];
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if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15_DATA_CACHE_LOCKDOWN];
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if (crn == 10 && opcode_1 == 0)
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{
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if (crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15_TLB_LOCKDOWN];
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if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_PRIMARY_REGION_REMAP];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_NORMAL_REGION_REMAP];
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}
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}
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if (crn == 13 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_PID];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_CONTEXT_ID];
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if (opcode_2 == 4)
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return cpu->CP15[CP15_THREAD_PRW];
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}
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if (crn == 15)
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{
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if (opcode_1 == 0 && crm == 12)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL];
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if (opcode_2 == 1)
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return cpu->CP15[CP15_CYCLE_COUNTER];
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if (opcode_2 == 2)
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return cpu->CP15[CP15_COUNT_0];
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if (opcode_2 == 3)
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return cpu->CP15[CP15_COUNT_1];
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}
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if (opcode_1 == 5 && opcode_2 == 2)
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{
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if (crm == 5)
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS];
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if (crm == 6)
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS];
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if (crm == 7)
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE];
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}
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if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
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return cpu->CP15[CP15_TLB_DEBUG_CONTROL];
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}
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}
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LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
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return 0;
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}
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// Write to the CP15 registers. Used with implementation of the MCR instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
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{
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if (InAPrivilegedMode(cpu))
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{
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_CONTROL] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_AUXILIARY_CONTROL] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value;
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}
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else if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = value;
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}
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else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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{
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cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = value;
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}
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else if (crn == 5 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_FAULT_STATUS] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_INSTR_FAULT_STATUS] = value;
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}
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else if (crn == 6 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_FAULT_ADDRESS] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_WFAR] = value;
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}
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else if (crn == 7 && opcode_1 == 0)
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{
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if (crm == 0 && opcode_2 == 4)
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{
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cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value;
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}
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else if (crm == 4 && opcode_2 == 0)
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{
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// NOTE: Not entirely accurate. This should do permission checks.
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cpu->CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value);
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}
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else if (crm == 5)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_INVALIDATE_INSTR_CACHE] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value;
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else if (opcode_2 == 6)
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cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value;
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else if (opcode_2 == 7)
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cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value;
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}
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else if (crm == 6)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_INVALIDATE_DATA_CACHE] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
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}
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else if (crm == 7 && opcode_2 == 0)
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{
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cpu->CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value;
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}
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else if (crm == 10)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_CLEAN_DATA_CACHE] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value;
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}
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else if (crm == 14)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
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}
|
|
}
|
|
else if (crn == 8 && opcode_1 == 0)
|
|
{
|
|
LOG_WARNING(Core_ARM11, "TLB operations not fully implemented.");
|
|
|
|
if (crm == 5)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_INVALIDATE_ITLB] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value;
|
|
}
|
|
else if (crm == 6)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_INVALIDATE_DTLB] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value;
|
|
}
|
|
else if (crm == 7)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_INVALIDATE_UTLB] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value;
|
|
}
|
|
}
|
|
else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
|
|
{
|
|
cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = value;
|
|
}
|
|
else if (crn == 10 && opcode_1 == 0)
|
|
{
|
|
if (crm == 0 && opcode_2 == 0)
|
|
{
|
|
cpu->CP15[CP15_TLB_LOCKDOWN] = value;
|
|
}
|
|
else if (crm == 2)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_PRIMARY_REGION_REMAP] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_NORMAL_REGION_REMAP] = value;
|
|
}
|
|
}
|
|
else if (crn == 13 && opcode_1 == 0 && crm == 0)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_PID] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_CONTEXT_ID] = value;
|
|
else if (opcode_2 == 3)
|
|
cpu->CP15[CP15_THREAD_URO] = value;
|
|
else if (opcode_2 == 4)
|
|
cpu->CP15[CP15_THREAD_PRW] = value;
|
|
}
|
|
else if (crn == 15)
|
|
{
|
|
if (opcode_1 == 0 && crm == 12)
|
|
{
|
|
if (opcode_2 == 0)
|
|
cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value;
|
|
else if (opcode_2 == 1)
|
|
cpu->CP15[CP15_CYCLE_COUNTER] = value;
|
|
else if (opcode_2 == 2)
|
|
cpu->CP15[CP15_COUNT_0] = value;
|
|
else if (opcode_2 == 3)
|
|
cpu->CP15[CP15_COUNT_1] = value;
|
|
}
|
|
else if (opcode_1 == 5)
|
|
{
|
|
if (crm == 4)
|
|
{
|
|
if (opcode_2 == 2)
|
|
cpu->CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
|
else if (opcode_2 == 4)
|
|
cpu->CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
|
}
|
|
else if (crm == 5 && opcode_2 == 2)
|
|
{
|
|
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value;
|
|
}
|
|
else if (crm == 6 && opcode_2 == 2)
|
|
{
|
|
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value;
|
|
}
|
|
else if (crm == 7 && opcode_2 == 2)
|
|
{
|
|
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value;
|
|
}
|
|
}
|
|
else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
|
|
{
|
|
cpu->CP15[CP15_TLB_DEBUG_CONTROL] = value;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Unprivileged registers
|
|
if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
|
|
{
|
|
cpu->CP15[CP15_FLUSH_PREFETCH_BUFFER] = value;
|
|
}
|
|
else if (crn == 7 && opcode_1 == 0 && crm == 10)
|
|
{
|
|
if (opcode_2 == 4)
|
|
cpu->CP15[CP15_DATA_SYNC_BARRIER] = value;
|
|
else if (opcode_2 == 5)
|
|
cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value;
|
|
|
|
}
|
|
else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
|
|
{
|
|
cpu->CP15[CP15_THREAD_UPRW] = value;
|
|
}
|
|
}
|