104 lines
3.6 KiB
C++
104 lines
3.6 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra::Shader {
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enum class OutputTopology : u32 {
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PointList = 1,
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LineStrip = 6,
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TriangleStrip = 7,
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};
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// Documentation in:
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// http://download.nvidia.com/open-gpu-doc/Shader-Program-Header/1/Shader-Program-Header.html#ImapTexture
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struct Header {
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union {
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BitField<0, 5, u32> sph_type;
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BitField<5, 5, u32> version;
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BitField<10, 4, u32> shader_type;
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BitField<14, 1, u32> mrt_enable;
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BitField<15, 1, u32> kills_pixels;
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BitField<16, 1, u32> does_global_store;
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BitField<17, 4, u32> sass_version;
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BitField<21, 5, u32> reserved;
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BitField<26, 1, u32> does_load_or_store;
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BitField<27, 1, u32> does_fp64;
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BitField<28, 4, u32> stream_out_mask;
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} common0;
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union {
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BitField<0, 24, u32> shader_local_memory_low_size;
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BitField<24, 8, u32> per_patch_attribute_count;
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} common1;
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union {
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BitField<0, 24, u32> shader_local_memory_high_size;
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BitField<24, 8, u32> threads_per_input_primitive;
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} common2;
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union {
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BitField<0, 24, u32> shader_local_memory_crs_size;
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BitField<24, 4, OutputTopology> output_topology;
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BitField<28, 4, u32> reserved;
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} common3;
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union {
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BitField<0, 12, u32> max_output_vertices;
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BitField<12, 8, u32> store_req_start; // NOTE: not used by geometry shaders.
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BitField<24, 4, u32> reserved;
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BitField<12, 8, u32> store_req_end; // NOTE: not used by geometry shaders.
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} common4;
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union {
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struct {
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INSERT_PADDING_BYTES(3); // ImapSystemValuesA
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INSERT_PADDING_BYTES(1); // ImapSystemValuesB
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INSERT_PADDING_BYTES(16); // ImapGenericVector[32]
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INSERT_PADDING_BYTES(2); // ImapColor
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INSERT_PADDING_BYTES(2); // ImapSystemValuesC
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INSERT_PADDING_BYTES(5); // ImapFixedFncTexture[10]
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INSERT_PADDING_BYTES(1); // ImapReserved
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INSERT_PADDING_BYTES(3); // OmapSystemValuesA
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INSERT_PADDING_BYTES(1); // OmapSystemValuesB
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INSERT_PADDING_BYTES(16); // OmapGenericVector[32]
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INSERT_PADDING_BYTES(2); // OmapColor
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INSERT_PADDING_BYTES(2); // OmapSystemValuesC
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INSERT_PADDING_BYTES(5); // OmapFixedFncTexture[10]
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INSERT_PADDING_BYTES(1); // OmapReserved
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} vtg;
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struct {
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INSERT_PADDING_BYTES(3); // ImapSystemValuesA
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INSERT_PADDING_BYTES(1); // ImapSystemValuesB
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INSERT_PADDING_BYTES(32); // ImapGenericVector[32]
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INSERT_PADDING_BYTES(2); // ImapColor
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INSERT_PADDING_BYTES(2); // ImapSystemValuesC
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INSERT_PADDING_BYTES(10); // ImapFixedFncTexture[10]
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INSERT_PADDING_BYTES(2); // ImapReserved
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struct {
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u32 target;
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union {
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BitField<0, 1, u32> sample_mask;
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BitField<1, 1, u32> depth;
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BitField<2, 30, u32> reserved;
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};
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} omap;
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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const u32 bit = render_target * 4 + component;
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return omap.target & (1 << bit);
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}
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} ps;
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};
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};
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static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
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} // namespace Tegra::Shader
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