Rasterizer: Document SignalFence & ReleaseFences and setup skeletons on Vulkan.
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@ -410,7 +410,6 @@ void Maxwell3D::ProcessQueryGet() {
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StampQueryResult(regs.query.query_sequence, regs.query.query_get.short_query == 0);
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StampQueryResult(regs.query.query_sequence, regs.query.query_get.short_query == 0);
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}
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}
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break;
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break;
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}
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case Regs::QueryOperation::Acquire:
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case Regs::QueryOperation::Acquire:
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// TODO(Blinkhawk): Under this operation, the GPU waits for the CPU to write a value that
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// TODO(Blinkhawk): Under this operation, the GPU waits for the CPU to write a value that
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// matches the current payload.
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// matches the current payload.
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@ -81,9 +81,12 @@ void ThreadManager::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
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}
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}
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void ThreadManager::FlushRegion(VAddr addr, u64 size) {
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void ThreadManager::FlushRegion(VAddr addr, u64 size) {
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if (!Settings::IsGPULevelExtreme()) {
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return;
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}
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if (system.Renderer().Rasterizer().MustFlushRegion(addr, size)) {
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if (system.Renderer().Rasterizer().MustFlushRegion(addr, size)) {
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u64 fence = PushCommand(FlushRegionCommand(addr, size));
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u64 fence = PushCommand(FlushRegionCommand(addr, size));
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while (fence < state.signaled_fence.load(std::memory_order_relaxed)) {
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while (fence > state.signaled_fence.load(std::memory_order_relaxed)) {
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}
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}
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}
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}
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}
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}
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@ -49,9 +49,11 @@ public:
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/// Records a GPU query and caches it
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/// Records a GPU query and caches it
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virtual void Query(GPUVAddr gpu_addr, QueryType type, std::optional<u64> timestamp) = 0;
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virtual void Query(GPUVAddr gpu_addr, QueryType type, std::optional<u64> timestamp) = 0;
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virtual void SignalFence(GPUVAddr addr, u32 value) {}
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/// Signal a GPU based fence
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virtual void SignalFence(GPUVAddr addr, u32 value) = 0;
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virtual void ReleaseFences() {}
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/// Release all pending fences.
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virtual void ReleaseFences() = 0;
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/// Notify rasterizer that all caches should be flushed to Switch memory
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/// Notify rasterizer that all caches should be flushed to Switch memory
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virtual void FlushAll() = 0;
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virtual void FlushAll() = 0;
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@ -535,6 +535,7 @@ void RasterizerVulkan::OnCPUWrite(VAddr addr, u64 size) {
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texture_cache.OnCPUWrite(addr, size);
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texture_cache.OnCPUWrite(addr, size);
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pipeline_cache.InvalidateRegion(addr, size);
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pipeline_cache.InvalidateRegion(addr, size);
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buffer_cache.OnCPUWrite(addr, size);
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buffer_cache.OnCPUWrite(addr, size);
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query_cache.InvalidateRegion(addr, size);
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}
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}
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void RasterizerVulkan::SyncGuestHost() {
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void RasterizerVulkan::SyncGuestHost() {
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@ -542,6 +543,30 @@ void RasterizerVulkan::SyncGuestHost() {
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buffer_cache.SyncGuestHost();
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buffer_cache.SyncGuestHost();
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}
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}
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void RasterizerVulkan::SignalFence(GPUVAddr addr, u32 value) {
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auto& gpu{system.GPU()};
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auto& memory_manager{gpu.MemoryManager()};
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memory_manager.Write<u32>(addr, value);
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/*
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if (!gpu.IsAsync()) {
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auto& memory_manager{gpu.MemoryManager()};
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memory_manager.Write<u32>(addr, value);
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return;
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}
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fence_manager.SignalFence(addr, value);
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*/
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}
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void RasterizerVulkan::ReleaseFences() {
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/*
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auto& gpu{system.GPU()};
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if (!gpu.IsAsync()) {
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return;
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}
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fence_manager.WaitPendingFences();
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*/
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}
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void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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FlushRegion(addr, size);
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FlushRegion(addr, size);
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InvalidateRegion(addr, size);
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InvalidateRegion(addr, size);
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@ -122,6 +122,8 @@ public:
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void InvalidateRegion(VAddr addr, u64 size) override;
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void InvalidateRegion(VAddr addr, u64 size) override;
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void OnCPUWrite(VAddr addr, u64 size) override;
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void OnCPUWrite(VAddr addr, u64 size) override;
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void SyncGuestHost() override;
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void SyncGuestHost() override;
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void SignalFence(GPUVAddr addr, u32 value) override;
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void ReleaseFences() override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void FlushCommands() override;
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void FlushCommands() override;
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void TickFrame() override;
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void TickFrame() override;
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