2021-02-06 02:11:23 +00:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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2021-02-08 05:54:35 +00:00
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#include <sirit/sirit.h>
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#include "common/common_types.h"
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2021-02-16 07:10:22 +00:00
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#include "shader_recompiler/backend/spirv/emit_context.h"
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2021-02-06 02:11:23 +00:00
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/frontend/ir/program.h"
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2021-02-20 06:30:13 +00:00
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#include "shader_recompiler/profile.h"
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2021-02-06 02:11:23 +00:00
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namespace Shader::Backend::SPIRV {
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2021-03-27 06:08:31 +00:00
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[[nodiscard]] std::vector<u32> EmitSPIRV(const Profile& profile, IR::Program& program,
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u32& binding);
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2021-02-08 05:54:35 +00:00
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2021-02-17 03:59:28 +00:00
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// Microinstruction emitters
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
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void EmitVoid(EmitContext& ctx);
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
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2021-03-19 22:28:31 +00:00
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void EmitBranch(EmitContext& ctx, Id label);
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void EmitBranchConditional(EmitContext& ctx, Id condition, Id true_label, Id false_label);
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void EmitLoopMerge(EmitContext& ctx, Id merge_label, Id continue_label);
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void EmitSelectionMerge(EmitContext& ctx, Id merge_label);
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2021-02-17 03:59:28 +00:00
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void EmitReturn(EmitContext& ctx);
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2021-03-27 21:30:24 +00:00
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void EmitUnreachable(EmitContext& ctx);
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2021-03-19 22:28:31 +00:00
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void EmitDemoteToHelperInvocation(EmitContext& ctx, Id continue_label);
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2021-04-04 06:04:48 +00:00
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void EmitBarrier(EmitContext& ctx);
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2021-04-17 06:21:03 +00:00
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void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
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void EmitDeviceMemoryBarrier(EmitContext& ctx);
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2021-03-24 04:33:45 +00:00
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void EmitPrologue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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2021-04-12 22:41:22 +00:00
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void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream);
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void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream);
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2021-02-17 03:59:28 +00:00
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void EmitGetRegister(EmitContext& ctx);
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void EmitSetRegister(EmitContext& ctx);
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void EmitGetPred(EmitContext& ctx);
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void EmitSetPred(EmitContext& ctx);
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void EmitSetGotoVariable(EmitContext& ctx);
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void EmitGetGotoVariable(EmitContext& ctx);
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2021-03-27 21:30:24 +00:00
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void EmitSetIndirectBranchVariable(EmitContext& ctx);
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void EmitGetIndirectBranchVariable(EmitContext& ctx);
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2021-03-09 20:14:57 +00:00
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Id EmitGetCbufU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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2021-04-04 05:31:09 +00:00
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Id EmitGetCbufU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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2021-04-12 22:41:22 +00:00
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, Id vertex);
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Id EmitGetAttributeIndexed(EmitContext& ctx, Id offset, Id vertex);
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void EmitSetAttributeIndexed(EmitContext& ctx, Id offset, Id value, Id vertex);
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2021-04-16 01:46:11 +00:00
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Id EmitGetPatch(EmitContext& ctx, IR::Patch patch);
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void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value);
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2021-03-19 22:28:31 +00:00
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void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value);
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2021-04-16 21:47:26 +00:00
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void EmitSetSampleMask(EmitContext& ctx, Id value);
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2021-03-19 22:28:31 +00:00
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void EmitSetFragDepth(EmitContext& ctx, Id value);
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2021-02-17 03:59:28 +00:00
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void EmitGetZFlag(EmitContext& ctx);
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void EmitGetSFlag(EmitContext& ctx);
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void EmitGetCFlag(EmitContext& ctx);
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void EmitGetOFlag(EmitContext& ctx);
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void EmitSetZFlag(EmitContext& ctx);
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void EmitSetSFlag(EmitContext& ctx);
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void EmitSetCFlag(EmitContext& ctx);
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void EmitSetOFlag(EmitContext& ctx);
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Id EmitWorkgroupId(EmitContext& ctx);
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Id EmitLocalInvocationId(EmitContext& ctx);
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2021-04-16 01:46:11 +00:00
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Id EmitInvocationId(EmitContext& ctx);
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2021-04-16 20:22:59 +00:00
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Id EmitSampleId(EmitContext& ctx);
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2021-04-11 22:16:12 +00:00
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Id EmitIsHelperInvocation(EmitContext& ctx);
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2021-04-16 21:52:58 +00:00
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Id EmitYDirection(EmitContext& ctx);
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2021-03-28 22:53:34 +00:00
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Id EmitLoadLocal(EmitContext& ctx, Id word_offset);
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void EmitWriteLocal(EmitContext& ctx, Id word_offset, Id value);
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2021-02-17 03:59:28 +00:00
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Id EmitUndefU1(EmitContext& ctx);
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Id EmitUndefU8(EmitContext& ctx);
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Id EmitUndefU16(EmitContext& ctx);
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Id EmitUndefU32(EmitContext& ctx);
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Id EmitUndefU64(EmitContext& ctx);
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void EmitLoadGlobalU8(EmitContext& ctx);
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void EmitLoadGlobalS8(EmitContext& ctx);
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void EmitLoadGlobalU16(EmitContext& ctx);
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void EmitLoadGlobalS16(EmitContext& ctx);
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void EmitLoadGlobal32(EmitContext& ctx);
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void EmitLoadGlobal64(EmitContext& ctx);
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void EmitLoadGlobal128(EmitContext& ctx);
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void EmitWriteGlobalU8(EmitContext& ctx);
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void EmitWriteGlobalS8(EmitContext& ctx);
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void EmitWriteGlobalU16(EmitContext& ctx);
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void EmitWriteGlobalS16(EmitContext& ctx);
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void EmitWriteGlobal32(EmitContext& ctx);
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void EmitWriteGlobal64(EmitContext& ctx);
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void EmitWriteGlobal128(EmitContext& ctx);
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2021-04-13 08:32:21 +00:00
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Id EmitLoadStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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2021-02-17 03:59:28 +00:00
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Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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2021-03-20 22:11:56 +00:00
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Id EmitLoadStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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2021-04-13 08:32:21 +00:00
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void EmitWriteStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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void EmitWriteStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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void EmitWriteStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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void EmitWriteStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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2021-02-17 03:59:28 +00:00
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void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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2021-02-19 21:10:18 +00:00
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void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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2021-03-08 21:31:53 +00:00
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void EmitWriteStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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2021-03-28 22:53:34 +00:00
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Id EmitLoadSharedU8(EmitContext& ctx, Id offset);
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Id EmitLoadSharedS8(EmitContext& ctx, Id offset);
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Id EmitLoadSharedU16(EmitContext& ctx, Id offset);
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Id EmitLoadSharedS16(EmitContext& ctx, Id offset);
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Id EmitLoadSharedU32(EmitContext& ctx, Id offset);
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Id EmitLoadSharedU64(EmitContext& ctx, Id offset);
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Id EmitLoadSharedU128(EmitContext& ctx, Id offset);
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void EmitWriteSharedU8(EmitContext& ctx, Id offset, Id value);
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void EmitWriteSharedU16(EmitContext& ctx, Id offset, Id value);
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void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value);
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void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value);
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void EmitWriteSharedU128(EmitContext& ctx, Id offset, Id value);
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2021-03-26 19:46:07 +00:00
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Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2);
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2021-02-19 21:10:18 +00:00
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Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
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Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
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Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeInsertU32x2(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertU32x3(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index);
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2021-03-26 19:46:07 +00:00
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Id EmitCompositeConstructF16x2(EmitContext& ctx, Id e1, Id e2);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeConstructF16x3(EmitContext& ctx, Id e1, Id e2, Id e3);
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Id EmitCompositeConstructF16x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
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2021-02-19 21:10:18 +00:00
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Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index);
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2021-03-26 19:46:07 +00:00
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Id EmitCompositeConstructF32x2(EmitContext& ctx, Id e1, Id e2);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeConstructF32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
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Id EmitCompositeConstructF32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
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2021-02-19 21:10:18 +00:00
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Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeInsertF32x2(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF32x3(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index);
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2021-02-17 03:59:28 +00:00
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void EmitCompositeConstructF64x2(EmitContext& ctx);
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void EmitCompositeConstructF64x3(EmitContext& ctx);
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void EmitCompositeConstructF64x4(EmitContext& ctx);
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void EmitCompositeExtractF64x2(EmitContext& ctx);
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void EmitCompositeExtractF64x3(EmitContext& ctx);
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void EmitCompositeExtractF64x4(EmitContext& ctx);
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2021-03-03 06:07:19 +00:00
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Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
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2021-03-08 03:01:22 +00:00
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Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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2021-02-23 01:59:16 +00:00
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Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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2021-03-21 23:28:37 +00:00
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Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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2021-02-17 03:59:28 +00:00
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void EmitBitCastU16F16(EmitContext& ctx);
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Id EmitBitCastU32F32(EmitContext& ctx, Id value);
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void EmitBitCastU64F64(EmitContext& ctx);
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void EmitBitCastF16U16(EmitContext& ctx);
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Id EmitBitCastF32U32(EmitContext& ctx, Id value);
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void EmitBitCastF64U64(EmitContext& ctx);
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2021-03-05 06:15:16 +00:00
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Id EmitPackUint2x32(EmitContext& ctx, Id value);
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2021-02-19 21:10:18 +00:00
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Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
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Id EmitPackFloat2x16(EmitContext& ctx, Id value);
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Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
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Id EmitPackHalf2x16(EmitContext& ctx, Id value);
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Id EmitUnpackHalf2x16(EmitContext& ctx, Id value);
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Id EmitPackDouble2x32(EmitContext& ctx, Id value);
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Id EmitUnpackDouble2x32(EmitContext& ctx, Id value);
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2021-02-17 03:59:28 +00:00
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void EmitGetZeroFromOp(EmitContext& ctx);
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void EmitGetSignFromOp(EmitContext& ctx);
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void EmitGetCarryFromOp(EmitContext& ctx);
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void EmitGetOverflowFromOp(EmitContext& ctx);
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2021-03-08 21:31:53 +00:00
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void EmitGetSparseFromOp(EmitContext& ctx);
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2021-03-25 15:31:37 +00:00
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void EmitGetInBoundsFromOp(EmitContext& ctx);
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2021-02-21 20:50:14 +00:00
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Id EmitFPAbs16(EmitContext& ctx, Id value);
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Id EmitFPAbs32(EmitContext& ctx, Id value);
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Id EmitFPAbs64(EmitContext& ctx, Id value);
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2021-02-17 03:59:28 +00:00
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Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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2021-03-14 06:23:56 +00:00
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Id EmitFPMax32(EmitContext& ctx, Id a, Id b);
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Id EmitFPMax64(EmitContext& ctx, Id a, Id b);
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Id EmitFPMin32(EmitContext& ctx, Id a, Id b);
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|
Id EmitFPMin64(EmitContext& ctx, Id a, Id b);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
|
|
|
|
Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
|
|
|
|
Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
2021-02-21 20:50:14 +00:00
|
|
|
Id EmitFPNeg16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPNeg32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPNeg64(EmitContext& ctx, Id value);
|
2021-02-23 01:59:16 +00:00
|
|
|
Id EmitFPSin(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPCos(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPExp2(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPLog2(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRecip32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRecip64(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRecipSqrt32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRecipSqrt64(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPSqrt(EmitContext& ctx, Id value);
|
2021-02-21 20:50:14 +00:00
|
|
|
Id EmitFPSaturate16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPSaturate32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPSaturate64(EmitContext& ctx, Id value);
|
2021-03-23 23:02:30 +00:00
|
|
|
Id EmitFPClamp16(EmitContext& ctx, Id value, Id min_value, Id max_value);
|
|
|
|
|
Id EmitFPClamp32(EmitContext& ctx, Id value, Id min_value, Id max_value);
|
|
|
|
|
Id EmitFPClamp64(EmitContext& ctx, Id value, Id min_value, Id max_value);
|
2021-02-19 21:10:18 +00:00
|
|
|
Id EmitFPRoundEven16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRoundEven32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPRoundEven64(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPFloor16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPFloor32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPFloor64(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPCeil16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPCeil32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPCeil64(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPTrunc16(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPTrunc32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFPTrunc64(EmitContext& ctx, Id value);
|
2021-02-23 01:59:16 +00:00
|
|
|
Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
|
2021-03-21 03:42:56 +00:00
|
|
|
Id EmitFPIsNan16(EmitContext& ctx, Id value);
|
2021-03-11 03:42:17 +00:00
|
|
|
Id EmitFPIsNan32(EmitContext& ctx, Id value);
|
2021-03-21 03:42:56 +00:00
|
|
|
Id EmitFPIsNan64(EmitContext& ctx, Id value);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
|
|
|
|
void EmitIAdd64(EmitContext& ctx);
|
|
|
|
|
Id EmitISub32(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
void EmitISub64(EmitContext& ctx);
|
|
|
|
|
Id EmitIMul32(EmitContext& ctx, Id a, Id b);
|
2021-02-22 05:45:50 +00:00
|
|
|
Id EmitINeg32(EmitContext& ctx, Id value);
|
2021-03-05 06:15:16 +00:00
|
|
|
Id EmitINeg64(EmitContext& ctx, Id value);
|
2021-02-22 05:45:50 +00:00
|
|
|
Id EmitIAbs32(EmitContext& ctx, Id value);
|
2021-03-20 08:04:12 +00:00
|
|
|
Id EmitIAbs64(EmitContext& ctx, Id value);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
|
2021-03-07 19:48:03 +00:00
|
|
|
Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
|
|
|
|
|
Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
|
|
|
|
|
Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
|
|
|
|
|
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
|
|
|
|
|
Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
|
2021-04-11 22:16:47 +00:00
|
|
|
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
|
|
|
|
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
|
|
|
|
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
|
2021-02-23 07:46:39 +00:00
|
|
|
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
|
2021-03-29 01:33:52 +00:00
|
|
|
Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
|
2021-03-08 03:01:22 +00:00
|
|
|
Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
|
2021-02-25 05:46:40 +00:00
|
|
|
Id EmitBitReverse32(EmitContext& ctx, Id value);
|
2021-02-27 02:41:46 +00:00
|
|
|
Id EmitBitCount32(EmitContext& ctx, Id value);
|
2021-03-01 20:58:16 +00:00
|
|
|
Id EmitBitwiseNot32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFindSMsb32(EmitContext& ctx, Id value);
|
|
|
|
|
Id EmitFindUMsb32(EmitContext& ctx, Id value);
|
2021-03-01 04:33:53 +00:00
|
|
|
Id EmitSMin32(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
Id EmitUMin32(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
Id EmitSMax32(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
Id EmitUMax32(EmitContext& ctx, Id a, Id b);
|
2021-03-29 01:33:52 +00:00
|
|
|
Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
|
|
|
|
|
Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
|
2021-02-21 20:50:14 +00:00
|
|
|
Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
|
2021-02-21 20:50:14 +00:00
|
|
|
Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs);
|
|
|
|
|
Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
|
2021-02-17 03:59:28 +00:00
|
|
|
Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
|
2021-04-11 06:07:02 +00:00
|
|
|
Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicSMin32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicUMin32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicSMax32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicUMax32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicInc32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicDec32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicAnd32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicOr32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicXor32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicExchange32(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitSharedAtomicExchange64(EmitContext& ctx, Id pointer_offset, Id value);
|
|
|
|
|
Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
|
Id value);
|
|
|
|
|
Id EmitGlobalAtomicIAdd32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicSMin32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicUMin32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicSMax32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicUMax32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicInc32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicDec32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicAnd32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicOr32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicXor32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicExchange32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicIAdd64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicSMin64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicUMin64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicSMax64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicUMax64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicInc64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicDec64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicAnd64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicOr64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicXor64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicExchange64(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicAddF32(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicAddF16x2(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicAddF32x2(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicMinF16x2(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicMinF32x2(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicMaxF16x2(EmitContext& ctx);
|
|
|
|
|
Id EmitGlobalAtomicMaxF32x2(EmitContext& ctx);
|
2021-02-22 02:42:38 +00:00
|
|
|
Id EmitLogicalOr(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b);
|
|
|
|
|
Id EmitLogicalXor(EmitContext& ctx, Id a, Id b);
|
|
|
|
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Id EmitLogicalNot(EmitContext& ctx, Id value);
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2021-02-19 21:10:18 +00:00
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Id EmitConvertS16F16(EmitContext& ctx, Id value);
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Id EmitConvertS16F32(EmitContext& ctx, Id value);
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Id EmitConvertS16F64(EmitContext& ctx, Id value);
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Id EmitConvertS32F16(EmitContext& ctx, Id value);
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Id EmitConvertS32F32(EmitContext& ctx, Id value);
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Id EmitConvertS32F64(EmitContext& ctx, Id value);
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Id EmitConvertS64F16(EmitContext& ctx, Id value);
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Id EmitConvertS64F32(EmitContext& ctx, Id value);
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Id EmitConvertS64F64(EmitContext& ctx, Id value);
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Id EmitConvertU16F16(EmitContext& ctx, Id value);
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Id EmitConvertU16F32(EmitContext& ctx, Id value);
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Id EmitConvertU16F64(EmitContext& ctx, Id value);
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Id EmitConvertU32F16(EmitContext& ctx, Id value);
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Id EmitConvertU32F32(EmitContext& ctx, Id value);
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Id EmitConvertU32F64(EmitContext& ctx, Id value);
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Id EmitConvertU64F16(EmitContext& ctx, Id value);
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Id EmitConvertU64F32(EmitContext& ctx, Id value);
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Id EmitConvertU64F64(EmitContext& ctx, Id value);
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Id EmitConvertU64U32(EmitContext& ctx, Id value);
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Id EmitConvertU32U64(EmitContext& ctx, Id value);
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2021-03-03 06:07:19 +00:00
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Id EmitConvertF16F32(EmitContext& ctx, Id value);
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Id EmitConvertF32F16(EmitContext& ctx, Id value);
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Id EmitConvertF32F64(EmitContext& ctx, Id value);
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Id EmitConvertF64F32(EmitContext& ctx, Id value);
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2021-03-20 08:04:12 +00:00
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Id EmitConvertF16S8(EmitContext& ctx, Id value);
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Id EmitConvertF16S16(EmitContext& ctx, Id value);
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2021-03-08 21:31:53 +00:00
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Id EmitConvertF16S32(EmitContext& ctx, Id value);
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Id EmitConvertF16S64(EmitContext& ctx, Id value);
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2021-03-20 08:04:12 +00:00
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Id EmitConvertF16U8(EmitContext& ctx, Id value);
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Id EmitConvertF16U16(EmitContext& ctx, Id value);
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2021-03-08 21:31:53 +00:00
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Id EmitConvertF16U32(EmitContext& ctx, Id value);
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Id EmitConvertF16U64(EmitContext& ctx, Id value);
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2021-03-20 08:04:12 +00:00
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Id EmitConvertF32S8(EmitContext& ctx, Id value);
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Id EmitConvertF32S16(EmitContext& ctx, Id value);
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2021-03-08 21:31:53 +00:00
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Id EmitConvertF32S32(EmitContext& ctx, Id value);
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Id EmitConvertF32S64(EmitContext& ctx, Id value);
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2021-03-20 08:04:12 +00:00
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Id EmitConvertF32U8(EmitContext& ctx, Id value);
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Id EmitConvertF32U16(EmitContext& ctx, Id value);
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2021-03-08 21:31:53 +00:00
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Id EmitConvertF32U32(EmitContext& ctx, Id value);
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Id EmitConvertF32U64(EmitContext& ctx, Id value);
|
2021-03-20 08:04:12 +00:00
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Id EmitConvertF64S8(EmitContext& ctx, Id value);
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Id EmitConvertF64S16(EmitContext& ctx, Id value);
|
2021-03-08 21:31:53 +00:00
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Id EmitConvertF64S32(EmitContext& ctx, Id value);
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Id EmitConvertF64S64(EmitContext& ctx, Id value);
|
2021-03-20 08:04:12 +00:00
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Id EmitConvertF64U8(EmitContext& ctx, Id value);
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Id EmitConvertF64U16(EmitContext& ctx, Id value);
|
2021-03-08 21:31:53 +00:00
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Id EmitConvertF64U32(EmitContext& ctx, Id value);
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Id EmitConvertF64U64(EmitContext& ctx, Id value);
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Id EmitBindlessImageSampleImplicitLod(EmitContext&);
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Id EmitBindlessImageSampleExplicitLod(EmitContext&);
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Id EmitBindlessImageSampleDrefImplicitLod(EmitContext&);
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Id EmitBindlessImageSampleDrefExplicitLod(EmitContext&);
|
2021-03-24 22:41:55 +00:00
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Id EmitBindlessImageGather(EmitContext&);
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Id EmitBindlessImageGatherDref(EmitContext&);
|
2021-03-26 18:24:50 +00:00
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Id EmitBindlessImageFetch(EmitContext&);
|
2021-03-26 21:45:38 +00:00
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Id EmitBindlessImageQueryDimensions(EmitContext&);
|
2021-03-28 17:47:52 +00:00
|
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Id EmitBindlessImageQueryLod(EmitContext&);
|
2021-03-29 00:00:43 +00:00
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Id EmitBindlessImageGradient(EmitContext&);
|
2021-04-09 04:45:39 +00:00
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Id EmitBindlessImageRead(EmitContext&);
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Id EmitBindlessImageWrite(EmitContext&);
|
2021-03-08 21:31:53 +00:00
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Id EmitBoundImageSampleImplicitLod(EmitContext&);
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Id EmitBoundImageSampleExplicitLod(EmitContext&);
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Id EmitBoundImageSampleDrefImplicitLod(EmitContext&);
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Id EmitBoundImageSampleDrefExplicitLod(EmitContext&);
|
2021-03-24 22:41:55 +00:00
|
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Id EmitBoundImageGather(EmitContext&);
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Id EmitBoundImageGatherDref(EmitContext&);
|
2021-03-26 18:24:50 +00:00
|
|
|
Id EmitBoundImageFetch(EmitContext&);
|
2021-03-26 21:45:38 +00:00
|
|
|
Id EmitBoundImageQueryDimensions(EmitContext&);
|
2021-03-28 17:47:52 +00:00
|
|
|
Id EmitBoundImageQueryLod(EmitContext&);
|
2021-03-29 00:00:43 +00:00
|
|
|
Id EmitBoundImageGradient(EmitContext&);
|
2021-04-09 04:45:39 +00:00
|
|
|
Id EmitBoundImageRead(EmitContext&);
|
|
|
|
|
Id EmitBoundImageWrite(EmitContext&);
|
2021-03-08 21:31:53 +00:00
|
|
|
Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
|
2021-04-17 05:59:54 +00:00
|
|
|
Id bias_lc, const IR::Value& offset);
|
2021-03-08 21:31:53 +00:00
|
|
|
Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
|
2021-04-17 05:59:54 +00:00
|
|
|
Id lod_lc, const IR::Value& offset);
|
2021-03-08 21:31:53 +00:00
|
|
|
Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
|
2021-04-17 05:59:54 +00:00
|
|
|
Id coords, Id dref, Id bias_lc, const IR::Value& offset);
|
2021-03-08 21:31:53 +00:00
|
|
|
Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
|
2021-04-17 05:59:54 +00:00
|
|
|
Id coords, Id dref, Id lod_lc, const IR::Value& offset);
|
2021-03-26 19:46:07 +00:00
|
|
|
Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
|
|
|
|
|
const IR::Value& offset, const IR::Value& offset2);
|
2021-03-24 22:41:55 +00:00
|
|
|
Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
|
2021-03-26 19:46:07 +00:00
|
|
|
const IR::Value& offset, const IR::Value& offset2, Id dref);
|
2021-03-26 18:24:50 +00:00
|
|
|
Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, Id offset,
|
|
|
|
|
Id lod, Id ms);
|
2021-03-26 21:45:38 +00:00
|
|
|
Id EmitImageQueryDimensions(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id lod);
|
2021-03-28 17:47:52 +00:00
|
|
|
Id EmitImageQueryLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords);
|
2021-03-29 00:00:43 +00:00
|
|
|
Id EmitImageGradient(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
|
|
|
|
|
Id derivates, Id offset, Id lod_clamp);
|
2021-04-09 04:45:39 +00:00
|
|
|
Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords);
|
|
|
|
|
void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, Id color);
|
2021-04-11 05:22:20 +00:00
|
|
|
Id EmitLaneId(EmitContext& ctx);
|
2021-03-24 00:27:17 +00:00
|
|
|
Id EmitVoteAll(EmitContext& ctx, Id pred);
|
|
|
|
|
Id EmitVoteAny(EmitContext& ctx, Id pred);
|
|
|
|
|
Id EmitVoteEqual(EmitContext& ctx, Id pred);
|
|
|
|
|
Id EmitSubgroupBallot(EmitContext& ctx, Id pred);
|
2021-04-04 08:17:17 +00:00
|
|
|
Id EmitSubgroupEqMask(EmitContext& ctx);
|
|
|
|
|
Id EmitSubgroupLtMask(EmitContext& ctx);
|
|
|
|
|
Id EmitSubgroupLeMask(EmitContext& ctx);
|
|
|
|
|
Id EmitSubgroupGtMask(EmitContext& ctx);
|
|
|
|
|
Id EmitSubgroupGeMask(EmitContext& ctx);
|
2021-03-25 15:31:37 +00:00
|
|
|
Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
|
|
|
|
|
Id segmentation_mask);
|
|
|
|
|
Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
|
|
|
|
|
Id segmentation_mask);
|
|
|
|
|
Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
|
|
|
|
|
Id segmentation_mask);
|
|
|
|
|
Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
|
|
|
|
|
Id segmentation_mask);
|
2021-03-29 02:23:45 +00:00
|
|
|
Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle);
|
2021-02-06 02:11:23 +00:00
|
|
|
|
2021-04-17 09:56:45 +00:00
|
|
|
Id EmitDPdxFine(EmitContext& ctx, Id op_a);
|
|
|
|
|
|
|
|
|
|
Id EmitDPdyFine(EmitContext& ctx, Id op_a);
|
|
|
|
|
|
2021-02-06 02:11:23 +00:00
|
|
|
} // namespace Shader::Backend::SPIRV
|
